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[committed] Fix reload problem using PA prefetch patterns


The following change fixes a reload problem with the prefetch patterns.
This was discovered when I fixed a typo in the previous implementation.
The prefetch patterns are new to 4.0.

The fix avoids using REG+D when a cache control completer needs to
be specified.  In this case, the dispacement D needs to be a 5-bit
displacement.  Other load/store insns use effectively a 14-bit
displacement.  At the moment, we have no way to tell these apart
in the reload process.  As a result, LEGITIMIZE_RELOAD_ADDRESS and
emit_move_sequence can't legitmize the address in prefetch insns
need a cache control completer.  I pondered creating a new mode for
this but this was going to take a fair bit of work to get right.

Tested on hppa64-hp-hpux11.11, hppa2.0w-hp-hpux11.11 and
hppa-unknown-linux-gnu.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)

2005-01-15  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* pa-protos.h (prefetch_operand): Delete.
	(prefetch_cc_operand, prefetch_nocc_operand): New declations.
	* pa.c (prefetch_operand): Delete.
	(prefetch_cc_operand, prefetch_nocc_operand): New functions.
	* pa.h (EXTRA_CONSTRAINT): Add `W' constraint.
	(PREDICATE_CODES): Delete prefetch_operand.  Add prefetch_cc_operand
	and prefetch_nocc_operand.
	* pa.md (prefetch): Rework to avoid reload problems handling short
	displacements when a cache control completer needs to be provided.
	(prefetch_32, prefetch_64): Delete.
	(prefetch_cc, prefetch_nocc): New patterns.

Index: config/pa/pa-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa-protos.h,v
retrieving revision 1.38
diff -u -3 -p -r1.38 pa-protos.h
--- config/pa/pa-protos.h	30 Dec 2004 03:08:00 -0000	1.38
+++ config/pa/pa-protos.h	15 Jan 2005 18:30:03 -0000
@@ -79,7 +79,8 @@ extern int arith_operand (rtx, enum mach
 extern int read_only_operand (rtx, enum machine_mode);
 extern int move_dest_operand (rtx, enum machine_mode);
 extern int move_src_operand (rtx, enum machine_mode);
-extern int prefetch_operand (rtx, enum machine_mode);
+extern int prefetch_cc_operand (rtx, enum machine_mode);
+extern int prefetch_nocc_operand (rtx, enum machine_mode);
 extern int and_operand (rtx, enum machine_mode);
 extern int ior_operand (rtx, enum machine_mode);
 extern int arith32_operand (rtx, enum machine_mode);
Index: config/pa/pa.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.c,v
retrieving revision 1.283
diff -u -3 -p -r1.283 pa.c
--- config/pa/pa.c	15 Jan 2005 17:10:01 -0000	1.283
+++ config/pa/pa.c	15 Jan 2005 18:30:04 -0000
@@ -752,24 +752,59 @@ move_src_operand (rtx op, enum machine_m
 }
 
 /* Accept anything that can be used as the source operand for a prefetch
-   instruction.  */
+   instruction with a cache-control completer.  */
+int
+prefetch_cc_operand (rtx op, enum machine_mode mode)
+{
+  if (GET_CODE (op) != MEM)
+    return 0;
+
+  op = XEXP (op, 0);
+
+  /* We must reject virtual registers as we don't allow REG+D.  */
+  if (op == virtual_incoming_args_rtx
+      || op == virtual_stack_vars_rtx
+      || op == virtual_stack_dynamic_rtx
+      || op == virtual_outgoing_args_rtx
+      || op == virtual_cfa_rtx)
+    return 0;
+
+  if (!REG_P (op) && !IS_INDEX_ADDR_P (op))
+    return 0;
+
+  /* Until problems with management of the REG_POINTER flag are resolved,
+     we need to delay creating prefetch insns with unscaled indexed addresses
+     until CSE is not expected.  */
+  if (!TARGET_NO_SPACE_REGS
+      && !cse_not_expected
+      && GET_CODE (op) == PLUS
+      && REG_P (XEXP (op, 0)))
+    return 0;
+
+  return memory_address_p (mode, op);
+}
+
+/* Accept anything that can be used as the source operand for a prefetch
+   instruction with no cache-control completer.  */
 int
-prefetch_operand (rtx op, enum machine_mode mode)
+prefetch_nocc_operand (rtx op, enum machine_mode mode)
 {
   if (GET_CODE (op) != MEM)
     return 0;
 
+  op = XEXP (op, 0);
+
   /* Until problems with management of the REG_POINTER flag are resolved,
      we need to delay creating prefetch insns with unscaled indexed addresses
      until CSE is not expected.  */
   if (!TARGET_NO_SPACE_REGS
       && !cse_not_expected
-      && GET_CODE (XEXP (op, 0)) == PLUS
-      && REG_P (XEXP (XEXP (op, 0), 0))
-      && REG_P (XEXP (XEXP (op, 0), 1)))
+      && GET_CODE (op) == PLUS
+      && REG_P (XEXP (op, 0))
+      && REG_P (XEXP (op, 1)))
     return 0;
 
-  return memory_address_p (mode, XEXP (op, 0));
+  return memory_address_p (mode, op);
 }
 
 /* Accept REG and any CONST_INT that can be moved in one instruction into a
Index: config/pa/pa.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.h,v
retrieving revision 1.239
diff -u -3 -p -r1.239 pa.h
--- config/pa/pa.h	30 Dec 2004 03:08:01 -0000	1.239
+++ config/pa/pa.h	15 Jan 2005 18:30:04 -0000
@@ -1296,7 +1296,12 @@ extern int may_call_alloca;
 
    `T' is for floating-point loads and stores.
 
-   `U' is the constant 63.  */
+   `U' is the constant 63.
+
+   `W' is a register indirect memory operand.  We could allow short
+       displacements but GO_IF_LEGITIMATE_ADDRESS can't tell when a
+       long displacement is valid.  This is only used for prefetch
+       instructions with the `sl' completer.  */
 
 #define EXTRA_CONSTRAINT(OP, C) \
   ((C) == 'Q' ?								\
@@ -1307,6 +1312,10 @@ extern int may_call_alloca;
 	&& !symbolic_memory_operand (OP, VOIDmode)			\
 	&& !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))				\
 	&& !IS_INDEX_ADDR_P (XEXP (OP, 0))))				\
+   : ((C) == 'W' ?							\
+      (GET_CODE (OP) == MEM						\
+       && REG_P (XEXP (OP, 0))						\
+       && REG_OK_FOR_BASE_P (XEXP (OP, 0)))				\
    : ((C) == 'A' ?							\
       (GET_CODE (OP) == MEM						\
        && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)))				\
@@ -1336,7 +1345,7 @@ extern int may_call_alloca;
    : ((C) == 'S' ?							\
       (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31)			\
    : ((C) == 'U' ?							\
-      (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0))))))
+      (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0)))))))
 	
 
 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
@@ -2102,7 +2111,8 @@ forget_section (void)							\
 				       CONST_DOUBLE}},			\
   {"move_dest_operand", {SUBREG, REG, MEM}},				\
   {"move_src_operand", {SUBREG, REG, CONST_INT, MEM}},			\
-  {"prefetch_operand", {MEM}},						\
+  {"prefetch_cc_operand", {MEM}},					\
+  {"prefetch_nocc_operand", {MEM}},					\
   {"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}},		\
   {"pic_label_operand", {LABEL_REF, CONST}},				\
   {"fp_reg_operand", {REG}},						\
Index: config/pa/pa.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.md,v
retrieving revision 1.155
diff -u -3 -p -r1.155 pa.md
--- config/pa/pa.md	1 Nov 2004 00:59:33 -0000	1.155
+++ config/pa/pa.md	15 Jan 2005 18:30:04 -0000
@@ -9283,134 +9283,88 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
    (match_operand 2 "const_int_operand" "")]
   "TARGET_PA_20"
 {
-  /* The PA 2.0 prefetch instructions only support short displacements
-     when a cache control completer needs to be supplied.  Thus, we
-     can't use LO_SUM DLT addresses with the spatial locality completer.  */
-  if (operands[2] == const0_rtx && IS_LO_SUM_DLT_ADDR_P (operands[0]))
-    FAIL;
-
-  /* We change operand0 to a MEM as we don't have the infrastructure to
-     output all the supported address modes for ldw/ldd but we do have
-     it for MEMs.  */
-  operands[0] = gen_rtx_MEM (Pmode, operands[0]);
-
-  if (!TARGET_NO_SPACE_REGS
-      && !cse_not_expected
-      && GET_CODE (XEXP (operands[0], 0)) == PLUS
-      && REG_P (XEXP (XEXP (operands[0], 0), 0))
-      && REG_P (XEXP (XEXP (operands[0], 0), 1)))
-    operands[0]
-      = replace_equiv_address (operands[0],
-			       copy_to_mode_reg (Pmode,
-					 	 XEXP (operands[0], 0)));
+  int locality = INTVAL (operands[2]);
+
+  if (locality < 0 || locality > 3)
+    abort ();
 
-  if (TARGET_64BIT)
-    emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2]));
+  /* Change operand[0] to a MEM as we don't have the infrastructure
+     to output all the supported address modes for ldw/ldd when we use
+     the address directly.  However, we do have it for MEMs.  */
+  operands[0] = gen_rtx_MEM (QImode, operands[0]);
+
+  /* If the address isn't valid for the prefetch, replace it.  */
+  if (locality)
+    {
+      if (!prefetch_nocc_operand (operands[0], QImode))
+	operands[0]
+	  = replace_equiv_address (operands[0],
+				   copy_to_mode_reg (Pmode,
+						     XEXP (operands[0], 0)));
+      emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
+    }
   else
-    emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2]));
+    {
+      if (!prefetch_cc_operand (operands[0], QImode))
+	operands[0]
+	  = replace_equiv_address (operands[0],
+				   copy_to_mode_reg (Pmode,
+						     XEXP (operands[0], 0)));
+      emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
+    }
   DONE;
 })
 
-(define_insn "prefetch_64"
-  [(prefetch (match_operand:DI 0 "prefetch_operand" "A,RQ")
-	     (match_operand:DI 1 "const_int_operand" "n,n")
-	     (match_operand:DI 2 "const_int_operand" "n,n"))]
-  "TARGET_64BIT
-   && (operands[2] != const0_rtx
-       || GET_CODE (XEXP (operands[0], 0)) != PLUS
-       || GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != CONST_INT
-       || INT_5_BITS (XEXP (XEXP (operands[0], 0), 1)))"
+(define_insn "prefetch_cc"
+  [(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
+	     (match_operand:SI 1 "const_int_operand" "n")
+	     (match_operand:SI 2 "const_int_operand" "n"))]
+  "TARGET_PA_20 && operands[2] == const0_rtx"
 {
-  /* The SL completor indicates good spatial locality but poor temporal
-     locality.  The ldw instruction with a target of general register 0
-     prefetches a cache line for a read.  The ldd instruction prefetches
-     a cache line for a write.  */
-  static const char * const instr[2][2][2] = {
-    {
-      {
-	"",
-	"ldw RT'%A0,%%r0",
-      },
-      {
-	"",
-	"ldd RT'%A0,%%r0",
-      },
-    },
-    {
-      {
-	"ldw%M0,sl %0,%%r0",
-	"ldw%M0 %0,%%r0",
-      },
-      {
-	"ldd%M0,sl %0,%%r0",
-	"ldd%M0 %0,%%r0",
-      }
-    }
+  /* The SL cache-control completor indicates good spatial locality but
+     poor temporal locality.  The ldw instruction with a target of general
+     register 0 prefetches a cache line for a read.  The ldd instruction
+     prefetches a cache line for a write.  */
+  static const char * const instr[2] = {
+    "ldw%M0,sl %0,%%r0",
+    "ldd%M0,sl %0,%%r0"
   };
   int read_or_write = INTVAL (operands[1]);
-  int locality = INTVAL (operands[2]);
 
-  if ((which_alternative != 0 && which_alternative != 1)
-      || (read_or_write != 0 && read_or_write != 1)
-      || (locality < 0 || locality > 3))
+  if (read_or_write < 0 || read_or_write > 1)
     abort ();
 
-  if (which_alternative == 0 && locality == 0)
-    abort ();
-
-  return instr [which_alternative][read_or_write][locality == 0 ? 0 : 1];
+  return instr [read_or_write];
 }
   [(set_attr "type" "load")
    (set_attr "length" "4")])
 
-(define_insn "prefetch_32"
-  [(prefetch (match_operand:SI 0 "prefetch_operand" "A,RQ")
+(define_insn "prefetch_nocc"
+  [(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
 	     (match_operand:SI 1 "const_int_operand" "n,n")
 	     (match_operand:SI 2 "const_int_operand" "n,n"))]
-  "TARGET_PA_20
-   && (operands[2] != const0_rtx
-       || GET_CODE (XEXP (operands[0], 0)) != PLUS
-       || GET_CODE (XEXP (XEXP (operands[0], 0), 1)) != CONST_INT
-       || INT_5_BITS (XEXP (XEXP (operands[0], 0), 1)))"
+  "TARGET_PA_20 && operands[2] != const0_rtx"
 {
-  /* The SL completor indicates good spatial locality but poor temporal
-     locality.  The ldw instruction with a target of general register 0
-     prefetches a cache line for a read.  The ldd instruction prefetches
-     a cache line for a write.  */
-  static const char * const instr[2][2][2] = {
+  /* The ldw instruction with a target of general register 0 prefetches
+     a cache line for a read.  The ldd instruction prefetches a cache line
+     for a write.  */
+  static const char * const instr[2][2] = {
     {
-      {
-	"",
-	"ldw RT'%A0,%%r0",
-      },
-      {
-	"",
-	"ldd RT'%A0,%%r0",
-      },
+      "ldw RT'%A0,%%r0",
+      "ldd RT'%A0,%%r0",
     },
     {
-      {
-	"ldw%M0,sl %0,%%r0",
-	"ldw%M0 %0,%%r0",
-      },
-      {
-	"ldd%M0,sl %0,%%r0",
-	"ldd%M0 %0,%%r0",
-      }
+      "ldw%M0 %0,%%r0",
+      "ldd%M0 %0,%%r0",
     }
   };
   int read_or_write = INTVAL (operands[1]);
-  int locality = INTVAL (operands[2]);
 
   if ((which_alternative != 0 && which_alternative != 1)
-      || (read_or_write != 0 && read_or_write != 1)
-      || (locality < 0 || locality > 3))
-    abort ();
-
-  if (which_alternative == 0 && locality == 0)
+      || (read_or_write < 0 || read_or_write > 1))
     abort ();
 
-  return instr [which_alternative][read_or_write][locality == 0 ? 0 : 1];
+  return instr [which_alternative][read_or_write];
 }
   [(set_attr "type" "load")
    (set_attr "length" "4")])


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