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[PATCH] Fix AVR backend bug, PR target/19329


Trivial fix for the "wrong-code" part of PR19329.

GCC 3.4 sometimes generates RTL code like this:

 (insn 46 65 49 (set (reg:QI 25 r25 [66])
        (ashift:QI (reg:QI 25 r25 [66])
            (const_int 0 [0x0]))) 57 {ashlqi3} (nil)

Even if shifts by 0 positions are somewhat bogus, the
documentation the for ashlqi3, ashrqui and lshrqi3 patterns
does not explicitly disallow it.  In this case the AVR backend
would inappropriately output a clr instruction (which is
otherwise correct for shifts 8 or more).

This patch only addresses the backend problem, so I think
this PR should remain open until someone else comes up with
a middle-end patch to eliminate the spurious shift.

Tested on mainline by comparing asm output on the test case
and a larger C application.  OK for mainline and 3.4?

Giovanni Bajo

2005-01-08  Bernardo Innocenti  <>
            Giovanni Bajo  <>
            Stefano Fedrigo  <>

        PR target/19329
        * config/avr/avr.c (ashlqi3_out, ashrqi3_out, lshrqi3_out): Handle
        shifts by 0 positions.

Attachment: gcc-3.4-PR19329-avr-0shift.patch
Description: Binary data

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