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ia64: Make unsigned-to-float conversions ABI conformant (PRtarget/7285)


When converting unsigned integers to floating point, the denormal
exception/
status must be prevented from being controlled by/going into fpsr.sf0.
Additionally, eventual other exceptions/status indicators (precision)
must
go into fpsr.sf0. Thus for conversions to SFmode and DFmode, a single
instruction cannot be used unless the user indicated no traps would be
of
interest (-fno-trapping-math), but instead the value must first be
converted
to XFmode under control of fpsr.sf1 and then to the destination mode
under
control of fpsr.sf0.

Bootstrapped and tested on ia64-unknown-linux-gnu.

Jan

gcc/
2005-01-06  Jan Beulich  <jbeulich@novell.com>

	PR target/7285
	* config/ia64/ia64.md (floatunsdisf2): Allow only when
	-fno-trapping-math. Use fpsr.sf1 as output status destination.
	(floatunsdidf2): Likewise.
	(floatunsdixf2): Use fpsr.sf1 as output status destination.

---
/home/jbeulich/src/gcc/mainline/2005-01-06.13.34/gcc/config/ia64/ia64.md	2005-01-04
09:22:55.000000000 +0100
+++ 2005-01-06.13.34/gcc/config/ia64/ia64.md	2005-01-07
08:32:25.649162389 +0100
@@ -972,22 +972,22 @@
 (define_insn "floatunsdisf2"
   [(set (match_operand:SF 0 "fr_register_operand" "=f")
 	(unsigned_float:SF (match_operand:DI 1 "fr_register_operand"
"f")))]
-  ""
-  "fcvt.xuf.s %0 = %1"
+  "!flag_trapping_math"
+  "fcvt.xuf.s.s1 %0 = %1"
   [(set_attr "itanium_class" "fcvtfx")])
 
 (define_insn "floatunsdidf2"
   [(set (match_operand:DF 0 "fr_register_operand" "=f")
 	(unsigned_float:DF (match_operand:DI 1 "fr_register_operand"
"f")))]
-  ""
-  "fcvt.xuf.d %0 = %1"
+  "!flag_trapping_math"
+  "fcvt.xuf.d.s1 %0 = %1"
   [(set_attr "itanium_class" "fcvtfx")])
 
 (define_insn "floatunsdixf2"
   [(set (match_operand:XF 0 "fr_register_operand" "=f")
 	(unsigned_float:XF (match_operand:DI 1 "fr_register_operand"
"f")))]
   ""
-  "fcvt.xuf %0 = %1"
+  "fcvt.xuf.s1 %0 = %1"
   [(set_attr "itanium_class" "fcvtfx")])
 
 (define_insn "fixuns_truncsfdi2"


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