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[altivec]Mode mode macros
- From: Nathan Sidwell <nathan at codesourcery dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>, Aldy Hernandez <aldyh at redhat dot com>
- Date: Wed, 24 Nov 2004 15:49:00 +0000
- Subject: [altivec]Mode mode macros
- Organization: Codesourcery LLC
This replaces more patterns with mode macros. I cleaned up
some instruction names that didn't play nicely, and changed the andc
pattern in line with what Dan Jacobowitz suggested.
booted & tested on ppc-unknown-linux-gnualtivec, ok?
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery LLC
nathan@codesourcery.com :: http://www.planetfall.pwp.blueyonder.co.uk
2004-11-24 Nathan Sidwell <nathan@codesourcery.com>
* config/rs6000/altivec.md (VIshort): New mode macro.
(altivec_vaddubs, altivec_vadduhs, altivec_vadduws): Replace
with ...
(altivec_vaddu<VI_char>s): ... this.
(altivec_vaddsbs, altivec_vaddshs, altivec_vaddsws): Replace
with ...
(altivec_vadds<VI_char>s): ... this.
(altivec_vsububs, altivec_vsubuhs, altivec_vsubuws): Replace
with ...
(altivec_vsubu<VI_char>s): ... this.
(altivec_vsubsbs, altivec_vsubshs, altivec_vsubsws): Replace
with ...
(altivec_vsubs<VI_char>s): ... this.
(altivec_vavgub, altivec_vavguh, altivec_vavguw): Replace
with ...
(altivec_vavgu<VI_char>): ... this.
(altivec_vavgsb, altivec_vavgsh, altivec_vavgsw): Replace
with ...
(altivec_vavgs<VI_char>): ... this.
(altivec_vmsumubm, altivec_vmsumuhm): Replace with ...
(altivec_vmsumu<VI_char>m): ... this.
(altivec_vmsummbm, altivec_vmsummhm): Replace
with ...
(altivec_vmsumm<VI_char>m): ... this.
(altivec_vandc): Remove.
(*andc<mode>3): Renamed to ...
(andc<mode>3): ... here. Swap operand 1 and 2 numbering.
(altivec_vrlb, altivec_vrlh, altivec_vrlw): Replace
with ...
(altivec_vrl<VI_char>): ... this.
(altivec_vslb, altivec_vslh, altivec_vslw): Replace
with ...
(altivec_vsl<VI_char>): ... this.
(altivec_vsrb, altivec_vsrh, altivec_vsrw): Replace
with ...
(altivec_vsr<VI_char>): ... this.
(altivec_vsrab, altivec_vsrah, altivec_vsraw): Replace
with ...
(altivec_vsra<VI_char>): ... this.
(altivec_vsum4sbs, altivec_vsum4shs): Replace with ...
(altivec_vsum4s<VI_char>s): ... this.
(altivec_vperm_4si, altivec_vperm_8hi, altivec_vperm_16qi): Replace
with ...
(altivec_vperm_<mode>): ... this.
(altivec_vsel_4sf): Rename to ...
(altivec_vsel_v4sf): ... here.
(altivec_vsel_4si, altivec_vsel_8hi, altivec_vsel_16qi): Replace
with ...
(altivec_vsel_<mode>): ... this.
(altivec_vsldoi_4si, altivec_vsldoi_8hi,
altivec_vsldoi_16qi): Rename to ...
(altivec_vsldoi_v4si, altivec_vsldoi_v8hi,
altivec_vsldoi_v16qi): ... here.
(altivec_vsldoi_4sf): Rename to ...
(altivec_vsldoi_v4sf): ... here.
(altivec_predicate_v4si, altivec_predicate_v8hi,
altivec_predicate_v16qi): Replace with ...
(altivec_predicate_<mode>): ... this.
(altivec_lvebx, altivec_lvehx, altivec_lvewx): Replace
with ...
(altivec_lve<VI_char>x): ... this.
(altivec_stvebx, altivec_stvehx, altivec_stvewx): Replace
with ...
(altivec_stve<VI_char>x): ... this.
(absv16qi2, absv8hi2, absv4si2): Replace
with ...
(abs<mode>2): ... this.
(altivec_abss_v16qi, altivec_abss_v8hi, altivec_abss_v4si): Replace
with ...
(altivec_abss_<mode>): ... this.
(vec_realign_load_v16qi, vec_realign_load_v8hi,
vec_realign_load_v4si): Replace with ...
(vec_realign_load_<mode>): ... this.
* config/rs6000/rs6000.c (bdesc_3arg, bdesc_2arg): Update tweaked
insn names.
(rs6000_expand_ternop_builtin): Likewise.
Index: config/rs6000/altivec.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/altivec.md,v
retrieving revision 1.28
diff -c -3 -p -r1.28 altivec.md
*** config/rs6000/altivec.md 22 Nov 2004 14:56:05 -0000 1.28
--- config/rs6000/altivec.md 24 Nov 2004 15:02:30 -0000
***************
*** 48,53 ****
--- 48,55 ----
;; Vec int modes
(define_mode_macro VI [V4SI V8HI V16QI])
+ ;; Short vec in modes
+ (define_mode_macro VIshort [V8HI V16QI])
;; Vec float modes
(define_mode_macro VF [V4SF])
;; Vec modes, pity mode macros are not composable
***************
*** 245,302 ****
"vaddcuw %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vaddubs"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 36))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vaddubs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vaddsbs"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 37))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vaddsbs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vadduhs"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 38))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vadduhs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vaddshs"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 39))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vaddshs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vadduws"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 40))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vadduws %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vaddsws"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 41))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vaddsws %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; sub
--- 247,268 ----
"vaddcuw %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vaddu<VI_char>s"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 36))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vaddu<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vadds<VI_char>s"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 37))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vadds<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
;; sub
***************
*** 324,430 ****
"vsubcuw %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsububs"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 125))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vsububs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsubsbs"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 126))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vsubsbs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsubuhs"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 127))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vsubuhs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsubshs"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 128))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vsubshs %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsubuws"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 129))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsubuws %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsubsws"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 130))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsubsws %0,%1,%2"
[(set_attr "type" "vecsimple")])
;;
! (define_insn "altivec_vavgub"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 44))]
! "TARGET_ALTIVEC"
! "vavgub %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vavgsb"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 45))]
! "TARGET_ALTIVEC"
! "vavgsb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vavguh"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 46))]
! "TARGET_ALTIVEC"
! "vavguh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vavgsh"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 47))]
! "TARGET_ALTIVEC"
! "vavgsh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vavguw"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 48))]
"TARGET_ALTIVEC"
! "vavguw %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vavgsw"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 49))]
"TARGET_ALTIVEC"
! "vavgsw %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpbfp"
--- 290,328 ----
"vsubcuw %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsubu<VI_char>s"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 125))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsubu<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsubs<VI_char>s"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 126))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsubs<VI_char>s %0,%1,%2"
[(set_attr "type" "vecsimple")])
;;
! (define_insn "altivec_vavgu<VI_char>"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 44))]
"TARGET_ALTIVEC"
! "vavgu<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vavgs<VI_char>"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 45))]
"TARGET_ALTIVEC"
! "vavgs<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vcmpbfp"
***************
*** 586,617 ****
"vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
!
! (define_insn "altivec_vmsumubm"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")
(match_operand:V4SI 3 "register_operand" "v")] 65))]
"TARGET_ALTIVEC"
! "vmsumubm %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
! (define_insn "altivec_vmsummbm"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")
(match_operand:V4SI 3 "register_operand" "v")] 66))]
"TARGET_ALTIVEC"
! "vmsummbm %0,%1,%2,%3"
! [(set_attr "type" "veccomplex")])
!
! (define_insn "altivec_vmsumuhm"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V4SI 3 "register_operand" "v")] 67))]
! "TARGET_ALTIVEC"
! "vmsumuhm %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
(define_insn "altivec_vmsumshm"
--- 484,505 ----
"vnmsubfp %0,%1,%2,%3"
[(set_attr "type" "vecfloat")])
! (define_insn "altivec_vmsumu<VI_char>m"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
! (match_operand:VIshort 2 "register_operand" "v")
(match_operand:V4SI 3 "register_operand" "v")] 65))]
"TARGET_ALTIVEC"
! "vmsumu<VI_char>m %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
! (define_insn "altivec_vmsumm<VI_char>m"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
! (match_operand:VIshort 2 "register_operand" "v")
(match_operand:V4SI 3 "register_operand" "v")] 66))]
"TARGET_ALTIVEC"
! "vmsumm<VI_char>m %0,%1,%2,%3"
[(set_attr "type" "veccomplex")])
(define_insn "altivec_vmsumshm"
***************
*** 936,955 ****
"vnor %0,%1,%2"
[(set_attr "type" "vecsimple")])
! ;; builtin_altivec_vandc (a, b) computes a & ~b, gcc's
! ;; canonicalization of that has the operands the other way round
! (define_expand "altivec_vandc"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (and:V4SI (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))
! (match_operand:V4SI 1 "register_operand" "v")))]
! "TARGET_ALTIVEC")
!
! (define_insn "*andc<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
! (and:VI (not:VI (match_operand:VI 1 "register_operand" "v"))
! (match_operand:VI 2 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vandc %0,%2,%1"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vpkuhum"
--- 824,835 ----
"vnor %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "andc<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
! (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
! (match_operand:VI 1 "register_operand" "v")))]
"TARGET_ALTIVEC"
! "vandc %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vpkuhum"
***************
*** 1048,1099 ****
"vpkswus %0,%1,%2"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vrlb"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 104))]
! "TARGET_ALTIVEC"
! "vrlb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vrlh"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 105))]
! "TARGET_ALTIVEC"
! "vrlh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vrlw"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 106))]
! "TARGET_ALTIVEC"
! "vrlw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vslb"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 107))]
! "TARGET_ALTIVEC"
! "vslb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vslh"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 108))]
"TARGET_ALTIVEC"
! "vslh %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vslw"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 109))]
"TARGET_ALTIVEC"
! "vslw %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vslw_v4sf"
--- 928,947 ----
"vpkswus %0,%1,%2"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vrl<VI_char>"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 104))]
"TARGET_ALTIVEC"
! "vrl<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsl<VI_char>"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 107))]
"TARGET_ALTIVEC"
! "vsl<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vslw_v4sf"
***************
*** 1120,1171 ****
"vslo %0,%1,%2"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsrb"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 112))]
! "TARGET_ALTIVEC"
! "vsrb %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsrh"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 113))]
! "TARGET_ALTIVEC"
! "vsrh %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsrw"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 114))]
! "TARGET_ALTIVEC"
! "vsrw %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsrab"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")] 115))]
! "TARGET_ALTIVEC"
! "vsrab %0,%1,%2"
! [(set_attr "type" "vecsimple")])
!
! (define_insn "altivec_vsrah"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")] 116))]
"TARGET_ALTIVEC"
! "vsrah %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsraw"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 117))]
"TARGET_ALTIVEC"
! "vsraw %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vsr"
--- 968,987 ----
"vslo %0,%1,%2"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsr<VI_char>"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 112))]
"TARGET_ALTIVEC"
! "vsr<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
! (define_insn "altivec_vsra<VI_char>"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 115))]
"TARGET_ALTIVEC"
! "vsra<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
(define_insn "altivec_vsr"
***************
*** 1193,1214 ****
"vsum4ubs %0,%1,%2"
[(set_attr "type" "veccomplex")])
! (define_insn "altivec_vsum4sbs"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 132))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsum4sbs %0,%1,%2"
! [(set_attr "type" "veccomplex")])
!
! (define_insn "altivec_vsum4shs"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")] 133))
! (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
! "TARGET_ALTIVEC"
! "vsum4shs %0,%1,%2"
[(set_attr "type" "veccomplex")])
(define_insn "altivec_vsum2sws"
--- 1009,1021 ----
"vsum4ubs %0,%1,%2"
[(set_attr "type" "veccomplex")])
! (define_insn "altivec_vsum4s<VI_char>s"
[(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")] 132))
(set (reg:SI 110) (unspec:SI [(const_int 0)] 213))]
"TARGET_ALTIVEC"
! "vsum4s<VI_char>s %0,%1,%2"
[(set_attr "type" "veccomplex")])
(define_insn "altivec_vsum2sws"
***************
*** 1299,1314 ****
"vrfiz %0,%1"
[(set_attr "type" "vecfloat")])
! (define_insn "altivec_vperm_4si"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
! (match_operand:V4SI 2 "register_operand" "v")
! (match_operand:V16QI 3 "register_operand" "v")] 144))]
! "TARGET_ALTIVEC"
! "vperm %0,%1,%2,%3"
! [(set_attr "type" "vecperm")])
!
! (define_insn "altivec_vperm_4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
--- 1106,1112 ----
"vrfiz %0,%1"
[(set_attr "type" "vecfloat")])
! (define_insn "altivec_vperm_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
***************
*** 1317,1336 ****
"vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vperm_8hi"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V16QI 3 "register_operand" "v")] 146))]
! "TARGET_ALTIVEC"
! "vperm %0,%1,%2,%3"
! [(set_attr "type" "vecperm")])
!
! (define_insn "altivec_vperm_16qi"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")
! (match_operand:V16QI 3 "register_operand" "v")] 147))]
"TARGET_ALTIVEC"
"vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
--- 1115,1125 ----
"vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vperm_<mode>"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")
! (match_operand:V16QI 3 "register_operand" "v")] 144))]
"TARGET_ALTIVEC"
"vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
***************
*** 1552,1558 ****
")
! (define_insn "altivec_vsel_4si"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")
--- 1341,1347 ----
")
! (define_insn "altivec_vsel_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")
***************
*** 1562,1568 ****
"vsel %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsel_4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
--- 1351,1357 ----
"vsel %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsel_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
***************
*** 1572,1578 ****
"vsel %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsel_8hi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
--- 1361,1367 ----
"vsel %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsel_v8hi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
***************
*** 1582,1588 ****
"vsel %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsel_16qi"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")
--- 1371,1377 ----
"vsel %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsel_v16qi"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")
***************
*** 1592,1598 ****
"vsel %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsldoi_4si"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")
--- 1381,1387 ----
"vsel %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsldoi_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=v")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
(match_operand:V4SI 2 "register_operand" "v")
***************
*** 1601,1607 ****
"vsldoi %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsldoi_4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
--- 1390,1396 ----
"vsldoi %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsldoi_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
(match_operand:V4SF 2 "register_operand" "v")
***************
*** 1610,1616 ****
"vsldoi %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsldoi_8hi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
--- 1399,1405 ----
"vsldoi %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsldoi_v8hi"
[(set (match_operand:V8HI 0 "register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
(match_operand:V8HI 2 "register_operand" "v")
***************
*** 1619,1625 ****
"vsldoi %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsldoi_16qi"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")
--- 1408,1414 ----
"vsldoi %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "altivec_vsldoi_v16qi"
[(set (match_operand:V16QI 0 "register_operand" "=v")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
(match_operand:V16QI 2 "register_operand" "v")
***************
*** 1705,1720 ****
;; We can get away with generating the opcode on the fly (%3 below)
;; because all the predicates have the same scheduling parameters.
- (define_insn "altivec_predicate_v4si"
- [(set (reg:CC 74)
- (unspec:CC [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")
- (match_operand 3 "any_operand" "")] 173))
- (clobber (match_scratch:V4SI 0 "=v"))]
- "TARGET_ALTIVEC"
- "%3 %0,%1,%2"
- [(set_attr "type" "veccmp")])
-
(define_insn "altivec_predicate_v4sf"
[(set (reg:CC 74)
(unspec:CC [(match_operand:V4SF 1 "register_operand" "v")
--- 1494,1499 ----
***************
*** 1725,1746 ****
"%3 %0,%1,%2"
[(set_attr "type" "veccmp")])
! (define_insn "altivec_predicate_v8hi"
[(set (reg:CC 74)
! (unspec:CC [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")
! (match_operand 3 "any_operand" "")] 175))
! (clobber (match_scratch:V8HI 0 "=v"))]
! "TARGET_ALTIVEC"
! "%3 %0,%1,%2"
! [(set_attr "type" "veccmp")])
!
! (define_insn "altivec_predicate_v16qi"
! [(set (reg:CC 74)
! (unspec:CC [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")
! (match_operand 3 "any_operand" "")] 175))
! (clobber (match_scratch:V16QI 0 "=v"))]
"TARGET_ALTIVEC"
"%3 %0,%1,%2"
[(set_attr "type" "veccmp")])
--- 1504,1515 ----
"%3 %0,%1,%2"
[(set_attr "type" "veccmp")])
! (define_insn "altivec_predicate_<mode>"
[(set (reg:CC 74)
! (unspec:CC [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")
! (match_operand 3 "any_operand" "")] 173))
! (clobber (match_scratch:VI 0 "=v"))]
"TARGET_ALTIVEC"
"%3 %0,%1,%2"
[(set_attr "type" "veccmp")])
***************
*** 1842,1872 ****
;; Parallel some of the LVE* and STV*'s with unspecs because some have
;; identical rtl but different instructions-- and gcc gets confused.
! (define_insn "altivec_lvebx"
[(parallel
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (match_operand:V16QI 1 "memory_operand" "m"))
(unspec [(const_int 0)] 196)])]
"TARGET_ALTIVEC"
! "lvebx %0,%y1"
! [(set_attr "type" "vecload")])
!
! (define_insn "altivec_lvehx"
! [(parallel
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (match_operand:V8HI 1 "memory_operand" "m"))
! (unspec [(const_int 0)] 197)])]
! "TARGET_ALTIVEC"
! "lvehx %0,%y1"
! [(set_attr "type" "vecload")])
!
! (define_insn "altivec_lvewx"
! [(parallel
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (match_operand:V4SI 1 "memory_operand" "m"))
! (unspec [(const_int 0)] 198)])]
! "TARGET_ALTIVEC"
! "lvewx %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvxl"
--- 1611,1623 ----
;; Parallel some of the LVE* and STV*'s with unspecs because some have
;; identical rtl but different instructions-- and gcc gets confused.
! (define_insn "altivec_lve<VI_char>x"
[(parallel
! [(set (match_operand:VI 0 "register_operand" "=v")
! (match_operand:VI 1 "memory_operand" "m"))
(unspec [(const_int 0)] 196)])]
"TARGET_ALTIVEC"
! "lve<VI_char>x %0,%y1"
[(set_attr "type" "vecload")])
(define_insn "altivec_lvxl"
***************
*** 1903,1962 ****
"stvxl %1,%y0"
[(set_attr "type" "vecstore")])
! (define_insn "altivec_stvebx"
[(parallel
! [(set (match_operand:V16QI 0 "memory_operand" "=m")
! (match_operand:V16QI 1 "register_operand" "v"))
(unspec [(const_int 0)] 203)])]
"TARGET_ALTIVEC"
! "stvebx %1,%y0"
! [(set_attr "type" "vecstore")])
!
! (define_insn "altivec_stvehx"
! [(parallel
! [(set (match_operand:V8HI 0 "memory_operand" "=m")
! (match_operand:V8HI 1 "register_operand" "v"))
! (unspec [(const_int 0)] 204)])]
! "TARGET_ALTIVEC"
! "stvehx %1,%y0"
[(set_attr "type" "vecstore")])
! (define_insn "altivec_stvewx"
! [(parallel
! [(set (match_operand:V4SI 0 "memory_operand" "=m")
! (match_operand:V4SI 1 "register_operand" "v"))
! (unspec [(const_int 0)] 205)])]
! "TARGET_ALTIVEC"
! "stvewx %1,%y0"
! [(set_attr "type" "vecstore")])
!
! (define_insn "absv16qi2"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (abs:V16QI (match_operand:V16QI 1 "register_operand" "v")))
! (clobber (match_scratch:V16QI 2 "=&v"))
! (clobber (match_scratch:V16QI 3 "=&v"))]
! "TARGET_ALTIVEC"
! "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3"
! [(set_attr "type" "vecsimple")
! (set_attr "length" "12")])
!
! (define_insn "absv8hi2"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (abs:V8HI (match_operand:V8HI 1 "register_operand" "v")))
! (clobber (match_scratch:V8HI 2 "=&v"))
! (clobber (match_scratch:V8HI 3 "=&v"))]
! "TARGET_ALTIVEC"
! "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3"
! [(set_attr "type" "vecsimple")
! (set_attr "length" "12")])
!
! (define_insn "absv4si2"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (abs:V4SI (match_operand:V4SI 1 "register_operand" "v")))
! (clobber (match_scratch:V4SI 2 "=&v"))
! (clobber (match_scratch:V4SI 3 "=&v"))]
"TARGET_ALTIVEC"
! "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3"
[(set_attr "type" "vecsimple")
(set_attr "length" "12")])
--- 1654,1675 ----
"stvxl %1,%y0"
[(set_attr "type" "vecstore")])
! (define_insn "altivec_stve<VI_char>x"
[(parallel
! [(set (match_operand:VI 0 "memory_operand" "=m")
! (match_operand:VI 1 "register_operand" "v"))
(unspec [(const_int 0)] 203)])]
"TARGET_ALTIVEC"
! "stve<VI_char>x %1,%y0"
[(set_attr "type" "vecstore")])
! (define_insn "abs<mode>2"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (abs:VI (match_operand:VI 1 "register_operand" "v")))
! (clobber (match_scratch:VI 2 "=&v"))
! (clobber (match_scratch:VI 3 "=&v"))]
"TARGET_ALTIVEC"
! "vspltisb %2,0\;vsubu<VI_char>m %3,%2,%1\;vmaxs<VI_char> %0,%1,%3"
[(set_attr "type" "vecsimple")
(set_attr "length" "12")])
***************
*** 1970,2014 ****
[(set_attr "type" "vecsimple")
(set_attr "length" "12")])
! (define_insn "altivec_abss_v16qi"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210))
! (clobber (match_scratch:V16QI 2 "=&v"))
! (clobber (match_scratch:V16QI 3 "=&v"))]
! "TARGET_ALTIVEC"
! "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3"
! [(set_attr "type" "vecsimple")
! (set_attr "length" "12")])
!
! (define_insn "altivec_abss_v8hi"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211))
! (clobber (match_scratch:V8HI 2 "=&v"))
! (clobber (match_scratch:V8HI 3 "=&v"))]
! "TARGET_ALTIVEC"
! "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3"
! [(set_attr "type" "vecsimple")
! (set_attr "length" "12")])
!
! (define_insn "altivec_abss_v4si"
! [(set (match_operand:V4SI 0 "register_operand" "=v")
! (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212))
! (clobber (match_scratch:V4SI 2 "=&v"))
! (clobber (match_scratch:V4SI 3 "=&v"))]
"TARGET_ALTIVEC"
! "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3"
[(set_attr "type" "vecsimple")
(set_attr "length" "12")])
- (define_insn "vec_realign_load_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=v")
- (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
- (match_operand:V4SI 2 "register_operand" "v")
- (match_operand:V16QI 3 "register_operand" "v")] 215))]
- "TARGET_ALTIVEC"
- "vperm %0,%1,%2,%3"
- [(set_attr "type" "vecperm")])
-
(define_insn "vec_realign_load_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
--- 1683,1698 ----
[(set_attr "type" "vecsimple")
(set_attr "length" "12")])
! (define_insn "altivec_abss_<mode>"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")] 210))
! (clobber (match_scratch:VI 2 "=&v"))
! (clobber (match_scratch:VI 3 "=&v"))]
"TARGET_ALTIVEC"
! "vspltisb %2,0\;vsubs<VI_char>s %3,%2,%1\;vmaxs<VI_char> %0,%1,%3"
[(set_attr "type" "vecsimple")
(set_attr "length" "12")])
(define_insn "vec_realign_load_v4sf"
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
***************
*** 2018,2038 ****
"vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "vec_realign_load_v8hi"
! [(set (match_operand:V8HI 0 "register_operand" "=v")
! (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
! (match_operand:V8HI 2 "register_operand" "v")
! (match_operand:V16QI 3 "register_operand" "v")] 217))]
! "TARGET_ALTIVEC"
! "vperm %0,%1,%2,%3"
! [(set_attr "type" "vecperm")])
!
! (define_insn "vec_realign_load_v16qi"
! [(set (match_operand:V16QI 0 "register_operand" "=v")
! (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
! (match_operand:V16QI 2 "register_operand" "v")
! (match_operand:V16QI 3 "register_operand" "v")] 218))]
"TARGET_ALTIVEC"
"vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
-
--- 1702,1712 ----
"vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
! (define_insn "vec_realign_load_<mode>"
! [(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")
! (match_operand:V16QI 3 "register_operand" "v")] 215))]
"TARGET_ALTIVEC"
"vperm %0,%1,%2,%3"
[(set_attr "type" "vecperm")])
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.751
diff -c -3 -p -r1.751 rs6000.c
*** config/rs6000/rs6000.c 22 Nov 2004 20:29:25 -0000 1.751
--- config/rs6000/rs6000.c 24 Nov 2004 15:02:32 -0000
*************** static const struct builtin_description
*** 6123,6140 ****
{ MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
! { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
! { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
};
/* DST operations: void foo (void *, const int, const char). */
--- 6123,6140 ----
{ MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
! { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
! { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
};
/* DST operations: void foo (void *, const int, const char). */
*************** static struct builtin_description bdesc_
*** 6163,6169 ****
{ MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
{ MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
! { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
--- 6163,6169 ----
{ MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
{ MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
{ MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
! { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
*************** rs6000_expand_ternop_builtin (enum insn_
*** 6922,6931 ****
|| arg2 == error_mark_node)
return const0_rtx;
! if (icode == CODE_FOR_altivec_vsldoi_4sf
! || icode == CODE_FOR_altivec_vsldoi_4si
! || icode == CODE_FOR_altivec_vsldoi_8hi
! || icode == CODE_FOR_altivec_vsldoi_16qi)
{
/* Only allow 4-bit unsigned literals. */
STRIP_NOPS (arg2);
--- 6922,6931 ----
|| arg2 == error_mark_node)
return const0_rtx;
! if (icode == CODE_FOR_altivec_vsldoi_v4sf
! || icode == CODE_FOR_altivec_vsldoi_v4si
! || icode == CODE_FOR_altivec_vsldoi_v8hi
! || icode == CODE_FOR_altivec_vsldoi_v16qi)
{
/* Only allow 4-bit unsigned literals. */
STRIP_NOPS (arg2);