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[PATCH] i386.md TARGET_USE_FANCY_MATH_387 clean-up
- From: Roger Sayle <roger at eyesopen dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 21 Nov 2004 13:12:00 -0700 (MST)
- Subject: [PATCH] i386.md TARGET_USE_FANCY_MATH_387 clean-up
It turns out that everywhere that the TARGET_NO_FANCY_MATH_387
macro is used in the i386.md backend, it always appears as the
idiom "! TARGET_NO_FANCY_MATH_387 && TARGET_80387". We can both
simplify and speed-up these tests by introducing a new macro in
i386.h "TARGET_USE_FANCY_MATH_387" with equivalent functionality.
The performance improvement comes from the realization that
! TARGET_80387 should automatically imply TARGET_NO_FANCY_MATH_387.
i.e. If we don't have an 387 or are using software emulation, we
should implicitly avoid generating x87 inline intrinsics. This
can be done efficiently once in i386.c's override_options at the
start of compilation, and avoid a more complex test everytime we
attempt to emit/recognize an x87 instruction.
This clean-up is actually a preparatory patch for a follow-up
functionality change to address a performance regression on
x86_64...
There should be absolutely no functionality change with this patch.
It has been tested on i686-pc-linux-gnu with a full "make bootstrap",
all default languages, and regression tested with a top-level "make
-k check" with no new failures.
Ok for mainline?
2004-11-21 Roger Sayle <roger@eyesopen.com>
* config/i386/i386.h (TARGET_USE_FANCY_MATH_387): New macro.
* config/i386/i386.c (override_options): Set MASK_NO_FANCY_MATH_387
automatically for targets without TARGET_80387.
* config/i386/i386.md (sqrtsf2, sqrtsf2_1, sqrtsf2_i387, sqrtdf2,
sqrtdf2_1, sqrtdf2_i387, *sqrtextendsfdf2, sqrtxf2,
*sqrtextenddfxf2, *sqrtextendsfxf2, fpremxf4, fmodsf3, fmoddf3,
fmodxf3, fprem1xf4, dremsf3, dremdf3, dremxf3, *sindf2, *sinsf2,
*sinextendsfdf2, *sinxf2, *cosdf2, *cossf2, *cosextendsfdf2,
*cosxf2, sincosdf3, sincossf3, *sincosextendsfdf3, sincosxf3,
*tandf3_1, tandf2, *tansf3_1, tansf2, *tanxf3_1, tanxf2,
atan2df3_1, atan2df3, atandf2, atan2sf3_1, atan2sf3, atansf2,
atan2xf3_1, atan2xf3, atanxf2, asindf2, asinsf2, asinxf2,
acosdf2, acossf2, acosxf2, fyl2x_xf3, logsf2, logdf2, logxf2,
log10sf2, log10df2, log10xf2, log2sf2, log2df2, log2xf2,
fyl2xp1_xf3, log1psf2, log1pdf2, log1pxf2, *fxtractxf3, logbsf2,
logbdf2, logbxf2, ilogbsi2, *f2xm1xf2, *fscalexf4, expsf2,
expdf2, expxf2, exp10sf2, exp10df2, exp10xf2, exp2sf2, exp2df2,
exp2xf2, expm1df2, expm1sf2, expm1xf2, frndintxf2, rintdf2,
rintsf2, rintxf2, frndintxf2_floor, floordf2, floorsf2,
floorxf2, frndintxf2_ceil, ceildf2, ceilsf2, ceilxf2,
frndintxf2_trunc, btruncdf2, btruncsf2, btruncxf2,
frndintxf2_mask_pm, nearbyintdf2, nearbyintsf2, nearbyintxf2):
Simplify conditionals using TARGET_USE_FANCY_MATH_387.
Index: i386.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.h,v
retrieving revision 1.403
diff -c -3 -p -r1.403 i386.h
*** i386.h 12 Nov 2004 21:15:23 -0000 1.403
--- i386.h 21 Nov 2004 17:53:48 -0000
*************** extern int target_flags;
*** 177,182 ****
--- 177,185 ----
This is because FreeBSD lacks these in the math-emulator-code */
#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387)
+ /* Generate 387 floating point intrinsics for the current target. */
+ #define TARGET_USE_FANCY_MATH_387 (! TARGET_NO_FANCY_MATH_387)
+
/* Don't create frame pointers for leaf functions */
#define TARGET_OMIT_LEAF_FRAME_POINTER \
(target_flags & MASK_OMIT_LEAF_FRAME_POINTER)
Index: i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.741
diff -c -3 -p -r1.741 i386.c
*** i386.c 18 Nov 2004 01:55:21 -0000 1.741
--- i386.c 21 Nov 2004 17:53:51 -0000
*************** override_options (void)
*** 1482,1487 ****
--- 1482,1492 ----
if (x86_arch_always_fancy_math_387 & (1 << ix86_arch))
target_flags &= ~MASK_NO_FANCY_MATH_387;
+ /* Likewise, if the target doesn't have a 387, or we've specified
+ software floating point, don't use 387 inline instrinsics. */
+ if (!TARGET_80387)
+ target_flags |= MASK_NO_FANCY_MATH_387;
+
/* Turn on SSE2 builtins for -msse3. */
if (TARGET_SSE3)
target_flags |= MASK_SSE2;
Index: i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.564
diff -c -3 -p -r1.564 i386.md
*** i386.md 18 Nov 2004 14:33:08 -0000 1.564
--- i386.md 21 Nov 2004 17:53:55 -0000
***************
*** 14844,14850 ****
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
! "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387) || TARGET_SSE_MATH"
{
if (!TARGET_SSE_MATH)
operands[1] = force_reg (SFmode, operands[1]);
--- 14844,14850 ----
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "register_operand" "")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "")))]
! "TARGET_USE_FANCY_MATH_387 || TARGET_SSE_MATH"
{
if (!TARGET_SSE_MATH)
operands[1] = force_reg (SFmode, operands[1]);
***************
*** 14853,14859 ****
(define_insn "sqrtsf2_1"
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
"@
fsqrt
--- 14853,14859 ----
(define_insn "sqrtsf2_1"
[(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
! "TARGET_USE_FANCY_MATH_387
&& (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
"@
fsqrt
***************
*** 14874,14880 ****
(define_insn "sqrtsf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& !TARGET_SSE_MATH"
"fsqrt"
[(set_attr "type" "fpspc")
--- 14874,14880 ----
(define_insn "sqrtsf2_i387"
[(set (match_operand:SF 0 "register_operand" "=f")
(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
! "TARGET_USE_FANCY_MATH_387
&& !TARGET_SSE_MATH"
"fsqrt"
[(set_attr "type" "fpspc")
***************
*** 14884,14890 ****
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
! "(! TARGET_NO_FANCY_MATH_387 && TARGET_80387)
|| (TARGET_SSE2 && TARGET_SSE_MATH)"
{
if (!TARGET_SSE2 || !TARGET_SSE_MATH)
--- 14884,14890 ----
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "register_operand" "")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
! "TARGET_USE_FANCY_MATH_387
|| (TARGET_SSE2 && TARGET_SSE_MATH)"
{
if (!TARGET_SSE2 || !TARGET_SSE_MATH)
***************
*** 14894,14900 ****
(define_insn "sqrtdf2_1"
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
"@
fsqrt
--- 14894,14900 ----
(define_insn "sqrtdf2_1"
[(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
! "TARGET_USE_FANCY_MATH_387
&& (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
"@
fsqrt
***************
*** 14915,14921 ****
(define_insn "sqrtdf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& (!TARGET_SSE2 || !TARGET_SSE_MATH)"
"fsqrt"
[(set_attr "type" "fpspc")
--- 14915,14921 ----
(define_insn "sqrtdf2_i387"
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
! "TARGET_USE_FANCY_MATH_387
&& (!TARGET_SSE2 || !TARGET_SSE_MATH)"
"fsqrt"
[(set_attr "type" "fpspc")
***************
*** 14926,14932 ****
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& !(TARGET_SSE2 && TARGET_SSE_MATH)"
"fsqrt"
[(set_attr "type" "fpspc")
--- 14926,14932 ----
[(set (match_operand:DF 0 "register_operand" "=f")
(sqrt:DF (float_extend:DF
(match_operand:SF 1 "register_operand" "0"))))]
! "TARGET_USE_FANCY_MATH_387
&& !(TARGET_SSE2 && TARGET_SSE_MATH)"
"fsqrt"
[(set_attr "type" "fpspc")
***************
*** 14936,14942 ****
(define_insn "sqrtxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
! "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
&& (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
"fsqrt"
[(set_attr "type" "fpspc")
--- 14936,14942 ----
(define_insn "sqrtxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (match_operand:XF 1 "register_operand" "0")))]
! "TARGET_USE_FANCY_MATH_387
&& (TARGET_IEEE_FP || flag_unsafe_math_optimizations) "
"fsqrt"
[(set_attr "type" "fpspc")
***************
*** 14947,14953 ****
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF
(match_operand:DF 1 "register_operand" "0"))))]
! "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
--- 14947,14953 ----
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF
(match_operand:DF 1 "register_operand" "0"))))]
! "TARGET_USE_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
***************
*** 14957,14963 ****
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))]
! "TARGET_80387 && !TARGET_NO_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
--- 14957,14963 ----
[(set (match_operand:XF 0 "register_operand" "=f")
(sqrt:XF (float_extend:XF
(match_operand:SF 1 "register_operand" "0"))))]
! "TARGET_USE_FANCY_MATH_387"
"fsqrt"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")
***************
*** 14973,14979 ****
UNSPEC_FPREM_U))
(set (reg:CCFP FPSR_REG)
(unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fprem"
[(set_attr "type" "fpspc")
--- 14973,14979 ----
UNSPEC_FPREM_U))
(set (reg:CCFP FPSR_REG)
(unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fprem"
[(set_attr "type" "fpspc")
***************
*** 14983,14989 ****
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))
(use (match_operand:SF 2 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
--- 14983,14989 ----
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))
(use (match_operand:SF 2 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
***************
*** 15007,15013 ****
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))
(use (match_operand:DF 2 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
--- 15007,15013 ----
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))
(use (match_operand:DF 2 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
***************
*** 15031,15037 ****
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))
(use (match_operand:XF 2 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
--- 15031,15037 ----
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))
(use (match_operand:XF 2 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
***************
*** 15056,15062 ****
UNSPEC_FPREM1_U))
(set (reg:CCFP FPSR_REG)
(unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fprem1"
[(set_attr "type" "fpspc")
--- 15056,15062 ----
UNSPEC_FPREM1_U))
(set (reg:CCFP FPSR_REG)
(unspec:CCFP [(const_int 0)] UNSPEC_NOP))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fprem1"
[(set_attr "type" "fpspc")
***************
*** 15066,15072 ****
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))
(use (match_operand:SF 2 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
--- 15066,15072 ----
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))
(use (match_operand:SF 2 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
***************
*** 15090,15096 ****
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))
(use (match_operand:DF 2 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
--- 15090,15096 ----
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))
(use (match_operand:DF 2 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
***************
*** 15114,15120 ****
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))
(use (match_operand:XF 2 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
--- 15114,15120 ----
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))
(use (match_operand:XF 2 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx label = gen_label_rtx ();
***************
*** 15132,15138 ****
(define_insn "*sindf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
--- 15132,15138 ----
(define_insn "*sindf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_SIN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
***************
*** 15141,15147 ****
(define_insn "*sinsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
--- 15141,15147 ----
(define_insn "*sinsf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_SIN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
***************
*** 15152,15158 ****
(unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))]
UNSPEC_SIN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
--- 15152,15158 ----
(unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))]
UNSPEC_SIN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
***************
*** 15161,15167 ****
(define_insn "*sinxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
! "TARGET_80387 && !TARGET_NO_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
--- 15161,15167 ----
(define_insn "*sinxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_SIN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsin"
[(set_attr "type" "fpspc")
***************
*** 15170,15176 ****
(define_insn "*cosdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
--- 15170,15176 ----
(define_insn "*cosdf2"
[(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 1 "register_operand" "0")] UNSPEC_COS))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
***************
*** 15179,15185 ****
(define_insn "*cossf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
--- 15179,15185 ----
(define_insn "*cossf2"
[(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 1 "register_operand" "0")] UNSPEC_COS))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
***************
*** 15190,15196 ****
(unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))]
UNSPEC_COS))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
--- 15190,15196 ----
(unspec:DF [(float_extend:DF
(match_operand:SF 1 "register_operand" "0"))]
UNSPEC_COS))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
***************
*** 15199,15205 ****
(define_insn "*cosxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
--- 15199,15205 ----
(define_insn "*cosxf2"
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")] UNSPEC_COS))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fcos"
[(set_attr "type" "fpspc")
***************
*** 15217,15223 ****
UNSPEC_SINCOS_COS))
(set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
--- 15217,15223 ----
UNSPEC_SINCOS_COS))
(set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
***************
*** 15251,15257 ****
UNSPEC_SINCOS_COS))
(set (match_operand:SF 1 "register_operand" "=u")
(unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
--- 15251,15257 ----
UNSPEC_SINCOS_COS))
(set (match_operand:SF 1 "register_operand" "=u")
(unspec:SF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
***************
*** 15287,15293 ****
(set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(float_extend:DF
(match_dup 2))] UNSPEC_SINCOS_SIN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
--- 15287,15293 ----
(set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(float_extend:DF
(match_dup 2))] UNSPEC_SINCOS_SIN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
***************
*** 15327,15333 ****
UNSPEC_SINCOS_COS))
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
--- 15327,15333 ----
UNSPEC_SINCOS_COS))
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fsincos"
[(set_attr "type" "fpspc")
***************
*** 15361,15367 ****
UNSPEC_TAN_ONE))
(set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fptan"
[(set_attr "type" "fpspc")
--- 15361,15367 ----
UNSPEC_TAN_ONE))
(set (match_operand:DF 1 "register_operand" "=u")
(unspec:DF [(match_dup 2)] UNSPEC_TAN_TAN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fptan"
[(set_attr "type" "fpspc")
***************
*** 15391,15397 ****
UNSPEC_TAN_ONE))
(set (match_operand:DF 0 "register_operand" "")
(unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (DFmode);
--- 15391,15397 ----
UNSPEC_TAN_ONE))
(set (match_operand:DF 0 "register_operand" "")
(unspec:DF [(match_dup 1)] UNSPEC_TAN_TAN))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (DFmode);
***************
*** 15403,15409 ****
UNSPEC_TAN_ONE))
(set (match_operand:SF 1 "register_operand" "=u")
(unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fptan"
[(set_attr "type" "fpspc")
--- 15403,15409 ----
UNSPEC_TAN_ONE))
(set (match_operand:SF 1 "register_operand" "=u")
(unspec:SF [(match_dup 2)] UNSPEC_TAN_TAN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fptan"
[(set_attr "type" "fpspc")
***************
*** 15433,15439 ****
UNSPEC_TAN_ONE))
(set (match_operand:SF 0 "register_operand" "")
(unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (SFmode);
--- 15433,15439 ----
UNSPEC_TAN_ONE))
(set (match_operand:SF 0 "register_operand" "")
(unspec:SF [(match_dup 1)] UNSPEC_TAN_TAN))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (SFmode);
***************
*** 15445,15451 ****
UNSPEC_TAN_ONE))
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fptan"
[(set_attr "type" "fpspc")
--- 15445,15451 ----
UNSPEC_TAN_ONE))
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_TAN_TAN))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fptan"
[(set_attr "type" "fpspc")
***************
*** 15475,15481 ****
UNSPEC_TAN_ONE))
(set (match_operand:XF 0 "register_operand" "")
(unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
--- 15475,15481 ----
UNSPEC_TAN_ONE))
(set (match_operand:XF 0 "register_operand" "")
(unspec:XF [(match_dup 1)] UNSPEC_TAN_TAN))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
***************
*** 15487,15493 ****
(match_operand:DF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 "=1"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
--- 15487,15493 ----
(match_operand:DF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 "=1"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
***************
*** 15497,15503 ****
[(use (match_operand:DF 0 "register_operand" "=f"))
(use (match_operand:DF 2 "register_operand" "0"))
(use (match_operand:DF 1 "register_operand" "u"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (DFmode);
--- 15497,15503 ----
[(use (match_operand:DF 0 "register_operand" "=f"))
(use (match_operand:DF 2 "register_operand" "0"))
(use (match_operand:DF 1 "register_operand" "u"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (DFmode);
***************
*** 15512,15518 ****
(match_operand:DF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 ""))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (DFmode);
--- 15512,15518 ----
(match_operand:DF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:DF 3 ""))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (DFmode);
***************
*** 15525,15531 ****
(match_operand:SF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 "=1"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
--- 15525,15531 ----
(match_operand:SF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 "=1"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
***************
*** 15535,15541 ****
[(use (match_operand:SF 0 "register_operand" "=f"))
(use (match_operand:SF 2 "register_operand" "0"))
(use (match_operand:SF 1 "register_operand" "u"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (SFmode);
--- 15535,15541 ----
[(use (match_operand:SF 0 "register_operand" "=f"))
(use (match_operand:SF 2 "register_operand" "0"))
(use (match_operand:SF 1 "register_operand" "u"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (SFmode);
***************
*** 15550,15556 ****
(match_operand:SF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 ""))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (SFmode);
--- 15550,15556 ----
(match_operand:SF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:SF 3 ""))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (SFmode);
***************
*** 15563,15569 ****
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 "=1"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
--- 15563,15569 ----
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 "=1"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
***************
*** 15573,15579 ****
[(use (match_operand:XF 0 "register_operand" "=f"))
(use (match_operand:XF 2 "register_operand" "0"))
(use (match_operand:XF 1 "register_operand" "u"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (XFmode);
--- 15573,15579 ----
[(use (match_operand:XF 0 "register_operand" "=f"))
(use (match_operand:XF 2 "register_operand" "0"))
(use (match_operand:XF 1 "register_operand" "u"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx copy = gen_reg_rtx (XFmode);
***************
*** 15588,15594 ****
(match_operand:XF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 ""))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
--- 15588,15594 ----
(match_operand:XF 1 "register_operand" "")]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 3 ""))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
***************
*** 15607,15613 ****
(clobber (match_scratch:XF 8 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 7)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
int i;
--- 15607,15613 ----
(clobber (match_scratch:XF 8 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 7)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
int i;
***************
*** 15630,15636 ****
(clobber (match_scratch:XF 8 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 7)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
int i;
--- 15630,15636 ----
(clobber (match_scratch:XF 8 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 7)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
int i;
***************
*** 15651,15657 ****
(unspec:XF [(match_dup 5) (match_dup 1)]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
int i;
--- 15651,15657 ----
(unspec:XF [(match_dup 5) (match_dup 1)]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
int i;
***************
*** 15674,15680 ****
(clobber (match_scratch:XF 8 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 7)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
int i;
--- 15674,15680 ----
(clobber (match_scratch:XF 8 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 7)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
int i;
***************
*** 15697,15703 ****
(clobber (match_scratch:XF 8 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 7)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
int i;
--- 15697,15703 ----
(clobber (match_scratch:XF 8 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 7)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
int i;
***************
*** 15718,15724 ****
(unspec:XF [(match_dup 1) (match_dup 5)]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
int i;
--- 15718,15724 ----
(unspec:XF [(match_dup 1) (match_dup 5)]
UNSPEC_FPATAN))
(clobber (match_scratch:XF 6 ""))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
int i;
***************
*** 15735,15741 ****
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 "=1"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fyl2x"
[(set_attr "type" "fpspc")
--- 15735,15741 ----
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 "=1"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fyl2x"
[(set_attr "type" "fpspc")
***************
*** 15750,15756 ****
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 15750,15756 ----
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 15772,15778 ****
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 15772,15778 ----
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 15790,15796 ****
(unspec:XF [(match_operand:XF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 15790,15796 ----
(unspec:XF [(match_operand:XF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 15809,15815 ****
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 15809,15815 ----
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 15831,15837 ****
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 15831,15837 ----
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 15849,15855 ****
(unspec:XF [(match_operand:XF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 15849,15855 ----
(unspec:XF [(match_operand:XF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 15868,15874 ****
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
--- 15868,15874 ----
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
***************
*** 15887,15893 ****
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
--- 15887,15893 ----
(clobber (match_scratch:XF 5 ""))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
***************
*** 15902,15908 ****
(unspec:XF [(match_operand:XF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
--- 15902,15908 ----
(unspec:XF [(match_operand:XF 1 "register_operand" "")
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_scratch:XF 3 ""))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
***************
*** 15915,15921 ****
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2XP1))
(clobber (match_scratch:XF 3 "=1"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fyl2xp1"
[(set_attr "type" "fpspc")
--- 15915,15921 ----
(match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2XP1))
(clobber (match_scratch:XF 3 "=1"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fyl2xp1"
[(set_attr "type" "fpspc")
***************
*** 15924,15930 ****
(define_expand "log1psf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 15924,15930 ----
(define_expand "log1psf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 15939,15945 ****
(define_expand "log1pdf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 15939,15945 ----
(define_expand "log1pdf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 15954,15960 ****
(define_expand "log1pxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
ix86_emit_i387_log1p (operands[0], operands[1]);
--- 15954,15960 ----
(define_expand "log1pxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
ix86_emit_i387_log1p (operands[0], operands[1]);
***************
*** 15967,15973 ****
UNSPEC_XTRACT_FRACT))
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fxtract"
[(set_attr "type" "fpspc")
--- 15967,15973 ----
UNSPEC_XTRACT_FRACT))
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fxtract"
[(set_attr "type" "fpspc")
***************
*** 15982,15988 ****
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
--- 15982,15988 ----
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 4)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
***************
*** 15999,16005 ****
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
--- 15999,16005 ----
(unspec:XF [(match_dup 2)] UNSPEC_XTRACT_EXP))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 4)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
***************
*** 16013,16019 ****
UNSPEC_XTRACT_FRACT))
(set (match_operand:XF 0 "register_operand" "")
(unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
--- 16013,16019 ----
UNSPEC_XTRACT_FRACT))
(set (match_operand:XF 0 "register_operand" "")
(unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
***************
*** 16028,16034 ****
(parallel [(set (match_operand:SI 0 "register_operand" "")
(fix:SI (match_dup 3)))
(clobber (reg:CC FLAGS_REG))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
--- 16028,16034 ----
(parallel [(set (match_operand:SI 0 "register_operand" "")
(fix:SI (match_dup 3)))
(clobber (reg:CC FLAGS_REG))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
***************
*** 16039,16045 ****
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_F2XM1))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"f2xm1"
[(set_attr "type" "fpspc")
--- 16039,16045 ----
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_F2XM1))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"f2xm1"
[(set_attr "type" "fpspc")
***************
*** 16053,16059 ****
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2) (match_dup 3)]
UNSPEC_FSCALE_EXP))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fscale"
[(set_attr "type" "fpspc")
--- 16053,16059 ----
(set (match_operand:XF 1 "register_operand" "=u")
(unspec:XF [(match_dup 2) (match_dup 3)]
UNSPEC_FSCALE_EXP))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fscale"
[(set_attr "type" "fpspc")
***************
*** 16075,16081 ****
UNSPEC_FSCALE_EXP))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 10)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 16075,16081 ----
UNSPEC_FSCALE_EXP))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 10)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 16104,16110 ****
UNSPEC_FSCALE_EXP))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 10)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 16104,16110 ----
UNSPEC_FSCALE_EXP))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 10)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 16130,16136 ****
(set (match_dup 9)
(unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_EXP))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 16130,16136 ----
(set (match_dup 9)
(unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_EXP))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 16159,16165 ****
UNSPEC_FSCALE_EXP))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 10)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 16159,16165 ----
UNSPEC_FSCALE_EXP))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 10)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 16188,16194 ****
UNSPEC_FSCALE_EXP))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 10)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 16188,16194 ----
UNSPEC_FSCALE_EXP))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 10)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 16214,16220 ****
(set (match_dup 9)
(unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_EXP))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 16214,16220 ----
(set (match_dup 9)
(unspec:XF [(match_dup 8) (match_dup 4)]
UNSPEC_FSCALE_EXP))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 16242,16248 ****
UNSPEC_FSCALE_EXP))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 8)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
int i;
--- 16242,16248 ----
UNSPEC_FSCALE_EXP))])
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 8)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
int i;
***************
*** 16267,16273 ****
UNSPEC_FSCALE_EXP))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 8)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
int i;
--- 16267,16273 ----
UNSPEC_FSCALE_EXP))])
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 8)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
int i;
***************
*** 16289,16295 ****
(set (match_dup 8)
(unspec:XF [(match_dup 7) (match_dup 3)]
UNSPEC_FSCALE_EXP))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
int i;
--- 16289,16295 ----
(set (match_dup 8)
(unspec:XF [(match_dup 7) (match_dup 3)]
UNSPEC_FSCALE_EXP))])]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
int i;
***************
*** 16322,16328 ****
(set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 14)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 16322,16328 ----
(set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
(set (match_operand:DF 0 "register_operand" "")
(float_truncate:DF (match_dup 14)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 16358,16364 ****
(set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 14)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 16358,16364 ----
(set (match_dup 14) (plus:XF (match_dup 13) (match_dup 8)))
(set (match_operand:SF 0 "register_operand" "")
(float_truncate:SF (match_dup 14)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 16392,16398 ****
(set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
(set (match_operand:XF 0 "register_operand" "")
(plus:XF (match_dup 12) (match_dup 7)))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx temp;
--- 16392,16398 ----
(set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9)))
(set (match_operand:XF 0 "register_operand" "")
(plus:XF (match_dup 12) (match_dup 7)))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx temp;
***************
*** 16410,16416 ****
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_FRNDINT))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"frndint"
[(set_attr "type" "fpspc")
--- 16410,16416 ----
[(set (match_operand:XF 0 "register_operand" "=f")
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_FRNDINT))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"frndint"
[(set_attr "type" "fpspc")
***************
*** 16419,16425 ****
(define_expand "rintdf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16419,16425 ----
(define_expand "rintdf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16435,16441 ****
(define_expand "rintsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16435,16441 ----
(define_expand "rintsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16451,16457 ****
(define_expand "rintxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
emit_insn (gen_frndintxf2 (operands[0], operands[1]));
--- 16451,16457 ----
(define_expand "rintxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
emit_insn (gen_frndintxf2 (operands[0], operands[1]));
***************
*** 16464,16470 ****
UNSPEC_FRNDINT_FLOOR))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint")
--- 16464,16470 ----
UNSPEC_FRNDINT_FLOOR))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint")
***************
*** 16474,16480 ****
(define_expand "floordf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16474,16480 ----
(define_expand "floordf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16494,16500 ****
(define_expand "floorsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16494,16500 ----
(define_expand "floorsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16514,16520 ****
(define_expand "floorxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op2 = assign_386_stack_local (HImode, 1);
--- 16514,16520 ----
(define_expand "floorxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op2 = assign_386_stack_local (HImode, 1);
***************
*** 16532,16538 ****
UNSPEC_FRNDINT_CEIL))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint")
--- 16532,16538 ----
UNSPEC_FRNDINT_CEIL))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint")
***************
*** 16542,16548 ****
(define_expand "ceildf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16542,16548 ----
(define_expand "ceildf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16562,16568 ****
(define_expand "ceilsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16562,16568 ----
(define_expand "ceilsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16582,16588 ****
(define_expand "ceilxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op2 = assign_386_stack_local (HImode, 1);
--- 16582,16588 ----
(define_expand "ceilxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op2 = assign_386_stack_local (HImode, 1);
***************
*** 16600,16606 ****
UNSPEC_FRNDINT_TRUNC))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint")
--- 16600,16606 ----
UNSPEC_FRNDINT_TRUNC))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfldcw\t%2"
[(set_attr "type" "frndint")
***************
*** 16610,16616 ****
(define_expand "btruncdf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16610,16616 ----
(define_expand "btruncdf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16630,16636 ****
(define_expand "btruncsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16630,16636 ----
(define_expand "btruncsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16650,16656 ****
(define_expand "btruncxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op2 = assign_386_stack_local (HImode, 1);
--- 16650,16656 ----
(define_expand "btruncxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op2 = assign_386_stack_local (HImode, 1);
***************
*** 16668,16674 ****
UNSPEC_FRNDINT_MASK_PM))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
[(set_attr "type" "frndint")
--- 16668,16674 ----
UNSPEC_FRNDINT_MASK_PM))
(use (match_operand:HI 2 "memory_operand" "m"))
(use (match_operand:HI 3 "memory_operand" "m"))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
"fldcw\t%3\n\tfrndint\n\tfclex\n\tfldcw\t%2"
[(set_attr "type" "frndint")
***************
*** 16678,16684 ****
(define_expand "nearbyintdf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16678,16684 ----
(define_expand "nearbyintdf2"
[(use (match_operand:DF 0 "register_operand" ""))
(use (match_operand:DF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16698,16704 ****
(define_expand "nearbyintsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
--- 16698,16704 ----
(define_expand "nearbyintsf2"
[(use (match_operand:SF 0 "register_operand" ""))
(use (match_operand:SF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op0 = gen_reg_rtx (XFmode);
***************
*** 16718,16724 ****
(define_expand "nearbyintxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
&& flag_unsafe_math_optimizations"
{
rtx op2 = assign_386_stack_local (HImode, 1);
--- 16718,16724 ----
(define_expand "nearbyintxf2"
[(use (match_operand:XF 0 "register_operand" ""))
(use (match_operand:XF 1 "register_operand" ""))]
! "TARGET_USE_FANCY_MATH_387
&& flag_unsafe_math_optimizations"
{
rtx op2 = assign_386_stack_local (HImode, 1);
Roger
--
Roger Sayle, E-mail: roger@eyesopen.com
OpenEye Scientific Software, WWW: http://www.eyesopen.com/
Suite 1107, 3600 Cerrillos Road, Tel: (+1) 505-473-7385
Santa Fe, New Mexico, 87507. Fax: (+1) 505-473-0833