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Re: [patch] SPARC VIS instructions or PR1820


>  I was having trouble with fand I think.  anddi_sp32_vis was being matched,
> but somehow the first set of contraints was matched, not the second, so the
> template to use was '#' which was causing trouble.

Probably because of the 32-bit calling conventions.  I think we must trust the 
compiler here, if the vector come in integer registers, it may be cheaper to 
use the integer logical instructions.

> > - the {AND,IOR,XOR} big splitter needs to be macroized too, because the
> > sp32 patterns piggyback on it for integer registers,
>
>  Is this only needed to use the cheapest set of instructions?

This is needed for correctness when V64 vectors are in integer registers in 
32-bit mode.  As for efficiency, we may need to disparage some alternatives 
but this would need to be studied.

>  I was wondering why combine said fnand cost twelve.  Thanks.

By default (i.e. unless overriden in sparc_rtx_costs), all operations cost 4.  
Since NAND is (ior (not) (not)), it ended up costing 12 vs 8 for (and)..(not).

>  That looks like what I was planning.  I'll probably end up working on them
> in a different order though.  I'd like to get intrinsics working first I
> think.

Fine with me. :-)

-- 
Eric Botcazou


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