This is the mail archive of the
mailing list for the GCC project.
Re: [RFC] PowerPC scheduling multi-instruction patterns
- From: Richard Henderson <rth at redhat dot com>
- To: David Edelsohn <dje at watson dot ibm dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Fri, 12 Nov 2004 17:21:06 -0800
- Subject: Re: [RFC] PowerPC scheduling multi-instruction patterns
- References: <200411092358.iA9NwoD30996@makai.watson.ibm.com>
On Tue, Nov 09, 2004 at 06:58:50PM -0500, David Edelsohn wrote:
> This patch improves the accuracy of the scheduling information for
> multi-instruction patterns. While I model the function unit occupancy, I
> am recording the latency as a single instruction. The multiple
> instructions are dependent and will not execute in parallel, so the latter
> instructions will occupy clock ticks and should not be modeled by the
> scheduler. The next RTL instruction that the scheduler can issue only
> should consider the latency of the last instruction. Comments?
This description makes no sense to me.
If the pattern will not execute in parallel, and the final instruction
in the pattern is issued two cycles after the first instruction in the
pattern, and the final instruction in the pattern has latency 1, then
it follows that the pattern as a whole has latency 3.