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Re: improve unaligned loads with no special insns


On Sun, Nov 07, 2004 at 10:33:36AM +0100, Eric Botcazou wrote:
> It apparently pessimizes on 32-bit targets for 4-byte unaligned loads:
...
> 2 more insns.

Hum.  I'm not sure how to gauge that then.  We need both offset
addressing and zero-extending byte loads for this to be shorter.
Which is true for sparc but not for ia64.

> Probably wrong on big-endian.  Something like:
> 
>   shift = BITS_PER_WORD - shift;
> 
> might be needed.

Looking at it.


r~


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