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[PATCH, committed] rs6000 tweaks


	This patch contains a couple of minor tweaks.

	PowerPC added a register-register subtract that does not set the
carry bit. This patch updates some SCC patterns to use it when the carry
result is not used.

	The rs6000_emit_move function was inserting unnecessary pseudos.
I decided to push this patch out while we're changing other parts of that
function.  A tweak for POWER4/5 latency calculations and a tweak to the
cost of a multiply by a constant.

David


	* config/rs6000/rs6000.md (scc patterns): Replace subfc with subf
	when carry not used.  Suggested by Torbjorn Granlund.

	* config/rs6000/rs6000.c (rs6000_emit_move): Don't force_reg
	operand[1] unnecessarily.  Suggested by Eric Christopher.
	(rs6000_adjust_cost): Increase latency of store to wider load.
	(rs6000_rtx_costs): mulli only allows 16-bit constants.

Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.327
diff -c -p -r1.327 rs6000.md
*** rs6000.md	27 Oct 2004 20:18:42 -0000	1.327
--- rs6000.md	5 Nov 2004 16:27:56 -0000
***************
*** 12623,12636 ****
    "")
  
  (define_insn ""
!   [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
! 	(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
! 		 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
    "TARGET_32BIT"
    "@
!   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
!   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
   [(set_attr "length" "12")])
  
  (define_insn ""
--- 12623,12638 ----
    "")
  
  (define_insn ""
!   [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
! 	(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
! 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
! 		 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))]
    "TARGET_32BIT"
    "@
!   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3
!   {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3
!   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3
!   {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3"
   [(set_attr "length" "12")])
  
  (define_insn ""
***************
*** 12643,12650 ****
     (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
    "TARGET_32BIT"
    "@
!    {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
!    {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
     #
     #"
    [(set_attr "type" "compare")
--- 12645,12652 ----
     (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
    "TARGET_32BIT"
    "@
!    {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
!    {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
     #
     #"
    [(set_attr "type" "compare")
***************
*** 12678,12685 ****
  	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
    "TARGET_32BIT"
    "@
!    {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
!    {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
     #
     #"
    [(set_attr "type" "compare")
--- 12680,12687 ----
  	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
    "TARGET_32BIT"
    "@
!    {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
!    {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
     #
     #"
    [(set_attr "type" "compare")
***************
*** 13539,13564 ****
    "")
  
  (define_insn ""
!   [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
! 	(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! 			 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
! 		 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
    "TARGET_32BIT"
    "@
     {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
!    {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
!   [(set_attr "length" "8,12")])
  
  (define_insn ""
!   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
! 	(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
! 			 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
! 		 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
    "TARGET_64BIT"
    "@
     addic %0,%1,%k2\;addze %0,%3
!    subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
!   [(set_attr "length" "8,12")])
  
  (define_insn ""
    [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
--- 13541,13568 ----
    "")
  
  (define_insn ""
!   [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r")
! 	(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
! 			 (match_operand:SI 2 "reg_or_short_operand" "I,rI,rI"))
! 		 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))]
    "TARGET_32BIT"
    "@
     {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
!    {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3
!    {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3"
!   [(set_attr "length" "8,12,12")])
  
  (define_insn ""
!   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r")
! 	(plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r")
! 			 (match_operand:DI 2 "reg_or_short_operand" "I,rI,rI"))
! 		 (match_operand:DI 3 "reg_or_short_operand" "r,r,I")))]
    "TARGET_64BIT"
    "@
     addic %0,%1,%k2\;addze %0,%3
!    subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf %0,%0,%3
!    subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfic %0,%0,%3"
!   [(set_attr "length" "8,12,12")])
  
  (define_insn ""
    [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
***************
*** 13571,13577 ****
    "TARGET_32BIT"
    "@
     {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
!    {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
     #
     #"
    [(set_attr "type" "compare")
--- 13575,13581 ----
    "TARGET_32BIT"
    "@
     {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
!    {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3
     #
     #"
    [(set_attr "type" "compare")
***************
*** 13605,13611 ****
    "TARGET_64BIT"
    "@
     addic %4,%1,%k2\;addze. %4,%3
!    subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
     #
     #"
    [(set_attr "type" "compare")
--- 13609,13615 ----
    "TARGET_64BIT"
    "@
     addic %4,%1,%k2\;addze. %4,%3
!    subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3
     #
     #"
    [(set_attr "type" "compare")
***************
*** 13640,13646 ****
    "TARGET_32BIT"
    "@
     {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
!    {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
     #
     #"
    [(set_attr "type" "compare")
--- 13644,13650 ----
    "TARGET_32BIT"
    "@
     {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
!    {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3
     #
     #"
    [(set_attr "type" "compare")
***************
*** 13675,13681 ****
    "TARGET_64BIT"
    "@
     addic %0,%1,%k2\;addze. %0,%3
!    subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
     #
     #"
    [(set_attr "type" "compare")
--- 13679,13685 ----
    "TARGET_64BIT"
    "@
     addic %0,%1,%k2\;addze. %0,%3
!    subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3
     #
     #"
    [(set_attr "type" "compare")
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.734
diff -c -p -r1.734 rs6000.c
*** rs6000.c	2 Nov 2004 09:50:28 -0000	1.734
--- rs6000.c	5 Nov 2004 16:28:10 -0000
*************** rs6000_emit_move (rtx dest, rtx source, 
*** 4264,4270 ****
        return;
      }
  
!   if (!no_new_pseudos && GET_CODE (operands[0]) != REG)
      operands[1] = force_reg (mode, operands[1]);
  
    if (mode == SFmode && ! TARGET_POWERPC
--- 4264,4271 ----
        return;
      }
  
!   if (!no_new_pseudos && GET_CODE (operands[0]) != REG
!       && !gpc_reg_operand (operands[1], mode))
      operands[1] = force_reg (mode, operands[1]);
  
    if (mode == SFmode && ! TARGET_POWERPC
*************** rs6000_adjust_cost (rtx insn, rtx link, 
*** 15735,15740 ****
--- 15736,15752 ----
      {
        /* Data dependency; DEP_INSN writes a register that INSN reads
  	 some cycles later.  */
+ 
+       /* Separate a load from a narrower, dependent store.  */
+       if (rs6000_sched_groups
+ 	  && GET_CODE (PATTERN (insn)) == SET
+ 	  && GET_CODE (PATTERN (dep_insn)) == SET
+ 	  && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
+ 	  && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
+ 	  && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
+ 	      > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
+ 	return cost + 14;
+ 
        switch (get_attr_type (insn))
  	{
  	case TYPE_JMPREG:
*************** rs6000_rtx_costs (rtx x, int code, int o
*** 17830,17836 ****
        return false;
  
      case MULT:
!       if (GET_CODE (XEXP (x, 1)) == CONST_INT)
  	{
  	  if (INTVAL (XEXP (x, 1)) >= -256
  	      && INTVAL (XEXP (x, 1)) <= 255)
--- 17842,17849 ----
        return false;
  
      case MULT:
!       if (GET_CODE (XEXP (x, 1)) == CONST_INT
! 	  && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
  	{
  	  if (INTVAL (XEXP (x, 1)) >= -256
  	      && INTVAL (XEXP (x, 1)) <= 255)


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