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Hi, this patch allows the sparc backend to generate VIS instructions for
vector operations. I've added the arithmetic VIS instructions. For any other
VIS instruction I've changed the mode to be created from a mode macro without
having to change anything. So far I've only tested this with bubblestraps
and running the tests that are attached. I'm running a bootstrap and
regtest now on sparc-linux. Then I'm going to do the same thing on
sparc64-linux. Ok for mainline if those work?
--
Thanks,
Jim
http://www.student.cs.uwaterloo.ca/~ja2morri/
http://phython.blogspot.com
http://open.nit.ca/wiki/?page=jim
gcc/ChangeLog:
2004-10-31 James A. Morrison <phython@gcc.gnu.org>
PR target/18230
* config/sparc/sparc-modes.def: Add vector modes of 4 and 8 bytes.
* config/sparc/sparc.c (sparc_vector_mode_supported_p): New function.
(TARGET_VECTOR_MODE_SUPPORTED_P): Set to sparc_vector_mode_supported_p.
(sparc_init_modes): Set sparc_mode_class to SF_MODE or DF_MODE for
MODE_VECTOR_INT and MODE_VECTOR_FLOAT.
* config/sparc/sparc.h: Define UNITS_PER_SIMD_WORD to 8 for TARGET_VIS.
* config/sparc/sparc.md (V64): New mode macro for 64 bit modes.
(V32): New mode macro for 32 bit modes.
(*movsf_insn_vis, movsf): Use V32 for modes instead of SF.
(movdf, *movdf_insn_v9only_vis, *modf_insn_sp64_vis): Use V64 for modes
instead of DF.
(V64I): New macro for 64 bit modes.
(V32I): New macro for 32 bit modes.
(anddi3, *anddi_sp32, *anddi_sp64, xordi3, *xordi_sp32, *xordi_sp64):
Use V64I for mode instead of DI.
(andsi3, *andsi_sp32, *andsi_sp64, xorsi3, *xorsi_sp32, *xorsi_sp64):
Use V32I for mode instead of SI.
(addv2si, subv2si, addv4hi, subv4hi, addv2hi, subv2hi): New patterns.
gcc/testsuite/ChangeLog:
2004-10-31 James A. Morrison <phython@gcc.gnu.org
PR target/18230
* gcc.target/sparc/fpadd16.c, gcc.target/sparc/fpadd16s.c,
gcc.target/sparc/fpsub16.c, gcc.target/sparc/fpsub16s.c,
gcc.target/sparc/fand.c, gcc.target/sparc/fands,
gcc.target/sparc/fxor.c, gcc.target/sparc/fxors.c,
gcc.target/sparc/fpadd32.c, gcc.target/sparc/fpsub32.c: New tests.
gcc/ChangeLog:
2004-10-31 James A. Morrison <phython@gcc.gnu.org>
PR target/18230
* config/sparc/sparc-modes.def: Add vector modes of 4 and 8 bytes.
* config/sparc/sparc.c (sparc_vector_mode_supported_p): New function.
(TARGET_VECTOR_MODE_SUPPORTED_P): Set to sparc_vector_mode_supported_p.
(sparc_init_modes): Set sparc_mode_class to SF_MODE or DF_MODE for
MODE_VECTOR_INT and MODE_VECTOR_FLOAT.
* config/sparc/sparc.h: Define UNITS_PER_SIMD_WORD to 8 for TARGET_VIS.
* config/sparc/sparc.md (V64): New mode macro for 64 bit modes.
(V32): New mode macro for 32 bit modes.
(*movsf_insn_vis, movsf): Use V32 for modes instead of SF.
(movdf, *movdf_insn_v9only_vis, *modf_insn_sp64_vis): Use V64 for modes
instead of DF.
(V64I): New macro for 64 bit modes.
(V32I): New macro for 32 bit modes.
(anddi3, *anddi_sp32, *anddi_sp64, xordi3, *xordi_sp32, *xordi_sp64):
Use V64I for mode instead of DI.
(andsi3, *andsi_sp32, *andsi_sp64, xorsi3, *xorsi_sp32, *xorsi_sp64):
Use V32I for mode instead of SI.
(addv2si, subv2si, addv4hi, subv4hi, addv2hi, subv2hi): New patterns.
gcc/testsuite/ChangeLog:
2004-10-31 James A. Morrison <phython@gcc.gnu.org
PR target/18230
* gcc.target/sparc/fpadd16.c, gcc.target/sparc/fpadd16s.c,
gcc.target/sparc/fpsub16.c, gcc.target/sparc/fpsub16s.c,
gcc.target/sparc/fand.c, gcc.target/sparc/fands,
gcc.target/sparc/fxor.c, gcc.target/sparc/fxors.c,
gcc.target/sparc/fpadd32.c, gcc.target/sparc/fpsub32.c: New tests.
Index: gcc/config/sparc/sparc-modes.def
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc-modes.def,v
retrieving revision 1.4
diff -u -p -r1.4 sparc-modes.def
--- gcc/config/sparc/sparc-modes.def 13 Oct 2003 21:16:32 -0000 1.4
+++ gcc/config/sparc/sparc-modes.def 31 Oct 2004 12:30:33 -0000
@@ -42,3 +42,7 @@ CC_MODE (CC_NOOV);
CC_MODE (CCX_NOOV);
CC_MODE (CCFP);
CC_MODE (CCFPE);
+
+/* Vector modes. */
+VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
+VECTOR_MODES (INT, 4); /* V4QI V2HI */
Index: gcc/config/sparc/sparc.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.c,v
retrieving revision 1.339
diff -u -p -r1.339 sparc.c
--- gcc/config/sparc/sparc.c 13 Oct 2004 14:04:29 -0000 1.339
+++ gcc/config/sparc/sparc.c 31 Oct 2004 12:30:37 -0000
@@ -348,6 +348,7 @@ static rtx sparc_struct_value_rtx (tree,
static bool sparc_return_in_memory (tree, tree);
static bool sparc_strict_argument_naming (CUMULATIVE_ARGS *);
static tree sparc_gimplify_va_arg (tree, tree, tree *, tree *);
+static bool sparc_vector_mode_supported_p(enum machine_mode);
static bool sparc_pass_by_reference (CUMULATIVE_ARGS *,
enum machine_mode, tree, bool);
#ifdef SUBTARGET_ATTRIBUTE_TABLE
@@ -466,6 +467,9 @@ enum processor_type sparc_cpu;
#undef TARGET_GIMPLIFY_VA_ARG_EXPR
#define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg
+#undef TARGET_VECTOR_MODE_SUPPORTED_P
+#define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p
+
#ifdef SUBTARGET_INSERT_ATTRIBUTES
#undef TARGET_INSERT_ATTRIBUTES
#define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
@@ -4181,6 +4182,13 @@ sparc_init_modes (void)
else
sparc_mode_class[i] = 0;
break;
+ case MODE_VECTOR_INT:
+ case MODE_VECTOR_FLOAT:
+ if (GET_MODE_SIZE (i) <= 4)
+ sparc_mode_class[i] = 1 << (int)SF_MODE;
+ else if (GET_MODE_SIZE (i) == 8)
+ sparc_mode_class[i] = 1 << (int)DF_MODE;
+ break;
case MODE_FLOAT:
case MODE_COMPLEX_FLOAT:
if (GET_MODE_SIZE (i) <= 4)
@@ -6106,6 +6099,17 @@ sparc_gimplify_va_arg (tree valist, tree
return build_va_arg_indirect_ref (addr);
}
+/* Vector modes are only supported with VIS. */
+static bool
+sparc_vector_mode_supported_p (enum machine_mode mode)
+{
+
+ if (TARGET_VIS && VECTOR_MODE_P (mode))
+ return true;
+ else
+ return false;
+}
+
/* Return the string to output an unconditional branch to LABEL, which is
the operand number of the label.
Index: gcc/config/sparc/sparc.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.h,v
retrieving revision 1.268
diff -u -p -r1.268 sparc.h
--- gcc/config/sparc/sparc.h 28 Sep 2004 06:26:08 -0000 1.268
+++ gcc/config/sparc/sparc.h 31 Oct 2004 12:30:38 -0000
@@ -769,6 +769,8 @@ extern struct sparc_cpu_select sparc_sel
#define MIN_UNITS_PER_WORD 4
#endif
+#define UNITS_PER_SIMD_WORD (TARGET_VIS ? 8 : 0)
+
/* Now define the sizes of the C data types. */
#define SHORT_TYPE_SIZE 16
Index: gcc/config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.md,v
retrieving revision 1.218
diff -u -p -r1.218 sparc.md
--- gcc/config/sparc/sparc.md 13 Oct 2004 14:04:30 -0000 1.218
+++ gcc/config/sparc/sparc.md 31 Oct 2004 12:30:42 -0000
@@ -2207,6 +2207,9 @@
[(set_attr "type" "*,*,*,load,store,fpmove,fpload,fpstore")
(set_attr "fptype" "*,*,*,*,*,double,*,*")])
+(define_mode_macro V64 [DF V4HI V8QI V2SI])
+(define_mode_macro V32 [SF V2HI V4QI])
+
(define_insn "*movdi_insn_sp64_vis"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W,b")
(match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e,J"))]
@@ -2627,12 +2630,12 @@
[(set_attr "type" "fpmove,*,*,*,*,load,fpload,fpstore,store")])
(define_insn "*movsf_insn_vis"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
- (match_operand:SF 1 "input_operand" "f,G,G,Q,*rR,S,m,m,f,*rG"))]
+ [(set (match_operand:V32 0 "nonimmediate_operand" "=f,f,*r,*r,*r,*r,*r,f,m,m")
+ (match_operand:V32 1 "input_operand" "f,G,G,Q,*rR,S,m,m,f,*rG"))]
"(TARGET_FPU && TARGET_VIS)
- && (register_operand (operands[0], SFmode)
- || register_operand (operands[1], SFmode)
- || fp_zero_operand (operands[1], SFmode))"
+ && (register_operand (operands[0], <V32:MODE>mode)
+ || register_operand (operands[1], <V32:MODE>mode)
+ || fp_zero_operand (operands[1], <V32:MODE>mode))"
{
if (GET_CODE (operands[1]) == CONST_DOUBLE
&& (which_alternative == 3
@@ -2756,9 +2759,9 @@
[(set (match_dup 0) (high:SF (match_dup 1)))
(set (match_dup 0) (lo_sum:SF (match_dup 0) (match_dup 1)))])
-(define_expand "movsf"
- [(set (match_operand:SF 0 "general_operand" "")
- (match_operand:SF 1 "general_operand" ""))]
+(define_expand "mov<V32:mode>"
+ [(set (match_operand:V32 0 "general_operand" "")
+ (match_operand:V32 1 "general_operand" ""))]
""
{
/* Force SFmode constants into memory. */
@@ -2818,9 +2821,9 @@
;
})
-(define_expand "movdf"
- [(set (match_operand:DF 0 "general_operand" "")
- (match_operand:DF 1 "general_operand" ""))]
+(define_expand "mov<V64:mode>"
+ [(set (match_operand:V64 0 "general_operand" "")
+ (match_operand:V64 1 "general_operand" ""))]
""
{
/* Force DFmode constants into memory. */
@@ -2969,14 +2972,14 @@
;; We have available v9 double floats but not 64-bit
;; integer registers but we have VIS.
(define_insn "*movdf_insn_v9only_vis"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o")
- (match_operand:DF 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGf"))]
+ [(set (match_operand:V64 0 "nonimmediate_operand" "=e,e,e,T,W,U,T,f,*r,o")
+ (match_operand:V64 1 "input_operand" "G,e,W#F,G,e,T,U,o#F,*roGF,*rGf"))]
"TARGET_FPU
&& TARGET_VIS
&& ! TARGET_ARCH64
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode)
- || fp_zero_operand (operands[1], DFmode))"
+ && (register_operand (operands[0], <V64:MODE>mode)
+ || register_operand (operands[1], <V64:MODE>mode)
+ || fp_zero_operand (operands[1], <V64:MODE>mode))"
"@
fzero\t%0
fmovd\t%1, %0
@@ -3018,14 +3021,14 @@
;; We have available both v9 double floats and 64-bit
;; integer registers. And we have VIS.
(define_insn "*movdf_insn_sp64_vis"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=e,e,e,W,*r,*r,m,*r")
- (match_operand:DF 1 "input_operand" "G,e,W#F,e,*rG,m,*rG,F"))]
+ [(set (match_operand:V64 0 "nonimmediate_operand" "=e,e,e,W,*r,*r,m,*r")
+ (match_operand:V64 1 "input_operand" "G,e,W#F,e,*rG,m,*rG,F"))]
"TARGET_FPU
&& TARGET_VIS
&& TARGET_ARCH64
- && (register_operand (operands[0], DFmode)
- || register_operand (operands[1], DFmode)
- || fp_zero_operand (operands[1], DFmode))"
+ && (register_operand (operands[0], <V64:MODE>mode)
+ || register_operand (operands[1], <V64:MODE>mode)
+ || fp_zero_operand (operands[1], <V64:MODE>mode))"
"@
fzero\t%0
fmovd\t%1, %0
@@ -5884,17 +5887,20 @@
;; We define DImode `and' so with DImode `not' we can get
;; DImode `andn'. Other combinations are possible.
-(define_expand "anddi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (and:DI (match_operand:DI 1 "arith_double_operand" "")
- (match_operand:DI 2 "arith_double_operand" "")))]
+(define_mode_macro V64I [DI V2SI V4HI V8QI])
+(define_mode_macro V32I [SI V2HI V4QI])
+
+(define_expand "and<V64I:mode>3"
+ [(set (match_operand:V64I 0 "register_operand" "")
+ (and:V64I (match_operand:V64I 1 "arith_double_operand" "")
+ (match_operand:V64I 2 "arith_double_operand" "")))]
""
"")
(define_insn "*anddi3_sp32"
- [(set (match_operand:DI 0 "register_operand" "=r,b")
- (and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
- (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+ [(set (match_operand:V64I 0 "register_operand" "=r,b")
+ (and:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
+ (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
"! TARGET_ARCH64"
"@
#
@@ -5904,9 +5910,9 @@
(set_attr "fptype" "double")])
(define_insn "*anddi3_sp64"
- [(set (match_operand:DI 0 "register_operand" "=r,b")
- (and:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
- (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+ [(set (match_operand:V64I 0 "register_operand" "=r,b")
+ (and:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
+ (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
"TARGET_ARCH64"
"@
and\t%1, %2, %0
@@ -5914,10 +5920,10 @@
[(set_attr "type" "*,fga")
(set_attr "fptype" "double")])
-(define_insn "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,d")
- (and:SI (match_operand:SI 1 "arith_operand" "%r,d")
- (match_operand:SI 2 "arith_operand" "rI,d")))]
+(define_insn "and<V32I:mode>3"
+ [(set (match_operand:V32I 0 "register_operand" "=r,d")
+ (and:V32I (match_operand:V32I 1 "arith_operand" "%r,d")
+ (match_operand:V32I 2 "arith_operand" "rI,d")))]
""
"@
and\t%1, %2, %0
@@ -6120,17 +6126,17 @@
fornot1s\t%1, %2, %0"
[(set_attr "type" "*,fga")])
-(define_expand "xordi3"
- [(set (match_operand:DI 0 "register_operand" "")
- (xor:DI (match_operand:DI 1 "arith_double_operand" "")
- (match_operand:DI 2 "arith_double_operand" "")))]
+(define_expand "xor<V64I:mode>3"
+ [(set (match_operand:V64I 0 "register_operand" "")
+ (xor:V64I (match_operand:V64I 1 "arith_double_operand" "")
+ (match_operand:V64I 2 "arith_double_operand" "")))]
""
"")
(define_insn "*xordi3_sp32"
- [(set (match_operand:DI 0 "register_operand" "=r,b")
- (xor:DI (match_operand:DI 1 "arith_double_operand" "%r,b")
- (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+ [(set (match_operand:V64I 0 "register_operand" "=r,b")
+ (xor:V64I (match_operand:V64I 1 "arith_double_operand" "%r,b")
+ (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
"! TARGET_ARCH64"
"@
#
@@ -6140,9 +6146,9 @@
(set_attr "fptype" "double")])
(define_insn "*xordi3_sp64"
- [(set (match_operand:DI 0 "register_operand" "=r,b")
- (xor:DI (match_operand:DI 1 "arith_double_operand" "%rJ,b")
- (match_operand:DI 2 "arith_double_operand" "rHI,b")))]
+ [(set (match_operand:V64I 0 "register_operand" "=r,b")
+ (xor:V64I (match_operand:V64I 1 "arith_double_operand" "%rJ,b")
+ (match_operand:V64I 2 "arith_double_operand" "rHI,b")))]
"TARGET_ARCH64"
"@
xor\t%r1, %2, %0
@@ -6158,10 +6164,10 @@
&& HOST_BITS_PER_WIDE_INT != 64)"
"xor\t%1, %2, %0")
-(define_insn "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=r,d")
- (xor:SI (match_operand:SI 1 "arith_operand" "%rJ,d")
- (match_operand:SI 2 "arith_operand" "rI,d")))]
+(define_insn "xor<V32I:mode>3"
+ [(set (match_operand:V32I 0 "register_operand" "=r,d")
+ (xor:V32I (match_operand:V32I 1 "arith_operand" "%rJ,d")
+ (match_operand:V32I 2 "arith_operand" "rI,d")))]
""
"@
xor\t%r1, %2, %0
@@ -8823,3 +8829,52 @@
"TARGET_TLS && TARGET_ARCH64"
"stx\t%0, [%1 + %2], %%tldo_add(%3)"
[(set_attr "type" "store")])
+
+;; VIS instructions
+(define_insn "addv2si3"
+ [(set (match_operand:V2SI 0 "register_operand" "=e")
+ (plus:V2SI (match_operand:V2SI 1 "register_operand" "e")
+ (match_operand:V2SI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpadd32\t%1, %2, %0"
+ [(set_attr "type" "fga")])
+
+(define_insn "subv2si3"
+ [(set (match_operand:V2SI 0 "register_operand" "=e")
+ (minus:V2SI (match_operand:V2SI 1 "register_operand" "e")
+ (match_operand:V2SI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpsub32\t%1, %2, %0"
+ [(set_attr "type" "fga")])
+
+(define_insn "addv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=e")
+ (plus:V4HI (match_operand:V4HI 1 "register_operand" "e")
+ (match_operand:V4HI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpadd16\t%1, %2, %0"
+ [(set_attr "type" "fga")])
+
+(define_insn "subv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=e")
+ (minus:V4HI (match_operand:V4HI 1 "register_operand" "e")
+ (match_operand:V4HI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpsub16\t%1, %2, %0"
+ [(set_attr "type" "fga")])
+
+(define_insn "addv2hi3"
+ [(set (match_operand:V2HI 0 "register_operand" "=f")
+ (plus:V2HI (match_operand:V2HI 1 "register_operand" "f")
+ (match_operand:V2HI 2 "register_operand" "f")))]
+ "TARGET_VIS"
+ "fpadd16s\t%1, %2, %0"
+ [(set_attr "type" "fga")])
+
+(define_insn "subv2hi3"
+ [(set (match_operand:V2HI 0 "register_operand" "=f")
+ (minus:V2HI (match_operand:V2HI 1 "register_operand" "f")
+ (match_operand:V2HI 2 "register_operand" "f")))]
+ "TARGET_VIS"
+ "fpsub16s\t%1, %2, %0"
+ [(set_attr "type" "fga")])
Attachment:
sparc.exp
Description: dg script
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef short vec16 __attribute__((vector_size(8)));
vec16 useless_function(vec16 a, vec16 b) {
return a + b;
}
/* { dg-final { scan-assembler "fpadd16\t%" } } */
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef short vec16 __attribute__((vector_size(4)));
vec16 useless_function(vec16 a, vec16 b) {
return a + b;
}
/* { dg-final { scan-assembler "fpadd16s\t%" } } */
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef short vec16 __attribute__((vector_size(4)));
vec16 useless_function(vec16 a, vec16 b) {
return a - b;
}
/* { dg-final { scan-assembler "fpsub16s\t%" } } */
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef short vec16 __attribute__((vector_size(8)));
vec16 useless_function(vec16 a, vec16 b) {
return a - b;
}
/* { dg-final { scan-assembler "fpsub16\t%" } } */
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef int vec32 __attribute__((vector_size(8)));
vec32 useless_function(vec32 a, vec32 b) {
return a + b;
}
/* { dg-final { scan-assembler "fpadd32\t%" } } */
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef int vec32 __attribute__((vector_size(8)));
vec32 useless_function(vec32 a, vec32 b) {
return a - b;
}
/* { dg-final { scan-assembler "fpsub32\t%" } } */
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef short vec16 __attribute__((vector_size(8)));
typedef short vec8 __attribute__((vector_size(8)));
typedef int vec32 __attribute__((vector_size(8)));
vec16 fun16(vec16 a, vec16 b) {
return a & b;
}
vec8 fun8(vec8 a, vec8 b) {
return a & b;
}
vec32 fun32(vec32 a, vec32 b) {
return a & b;
}
/* { dg-final { scan-assembler-times "fand" 4 } } */
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef short vec16 __attribute__((vector_size(4)));
typedef short vec8 __attribute__((vector_size(4)));
vec16 fun16(vec16 a, vec16 b) {
return a & b;
}
vec8 fun8(vec8 a, vec8 b) {
return a & b;
}
/* { dg-final { scan-assembler-times "fands" 3 } } */
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef short vec16 __attribute__((vector_size(4)));
typedef short vec8 __attribute__((vector_size(4)));
vec16 fun16(vec16 a, vec16 b) {
return a ^ b;
}
vec8 fun8(vec8 a, vec8 b) {
return a ^ b;
}
/* { dg-final { scan-assembler-times "fxors" 3 } } */
/* { dg-do compile } */
/* { dg-options "-mcpu=ultrasparc -mvis" } */
typedef short vec16 __attribute__((vector_size(8)));
typedef short vec8 __attribute__((vector_size(8)));
typedef int vec32 __attribute__((vector_size(8)));
vec16 fun16(vec16 a, vec16 b) {
return a ^ b;
}
vec8 fun8(vec8 a, vec8 b) {
return a ^ b;
}
vec32 fun32(vec32 a, vec32 b) {
return a ^ b;
}
/* { dg-final { scan-assembler-times "fxor" 4 } } */
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