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Re: [PATCH] x86 peephole2s to optimize "1LL << x"
On Sun, Sep 12, 2004 at 11:03:02PM +0200, Florian Weimer wrote:
> What about architectures with partial register stalls? The Pentium 4
> doesn't have them, but your A implementation might take a significant
> hit on the Pentium III (and probably Pentium M, too).
No, the ppro microarchitecture (includes p2,p3,pm) special-cases
xor reg,reg to indicate that the register is clear, which avoids
the partial register stall.
r~