Re: [rfc] coalesce stack slots

[Vladimir Makarov <vmakarov at redhat dot com>]

Roger Sayle wrote:

> On Tue, Sep 07, 2004 at 05:22:53PM -0400, Vladimir Makarov wrote:
>  
>
> > This weekend I got some SPECINT results for your patch for P4.  I've
> > checked -mtune=i386 and -march=i386/-mtune=pentium4.  I am sorry,
> > Richard but in overall the score with the patch results in about 0.5%
> > slower code.  I think freedom in insn scheduling (performed by P4) is
> > more important then better data locality for SPECINT.
> >    
>
> Perhaps adding a pipeline description for the Pentium4 to allow GCC
> to perform instruction scheduling might redress the issue?  I know
> that the Pentium4 supports out-of-order execution, and so subsumes
> simple instruction scheduling, but using a DFA can't hurt and might
> catch the more difficult cases.  We generate much more P4/scheduler
> friendly RTL now than we did the last time the experiment was tried.
>  
I worked on this several time.  I've tried several DFA p4 description 
form simple  to complex ones (differing forms of insns reading/storing 
memory) without any visible SPECINT2000 improvent.  It looks like P4 is 
very insensibile to insn scheduling.

Although, I've tried it for previous Nortwood core.  Probably it is time 
to try to do this for Prescott.

> It just seems strange to study the interaction between coalescing
> stack slots and instruction scheduling on two processors for which
> GCC doesn't do DFA scheduling...
>
>