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[committed] mips.md macroisation (9/n)

From: Richard Sandiford <rsandifo at redhat dot com>
To: gcc-patches at gcc dot gnu dot org
Date: Mon, 23 Aug 2004 09:20:11 +0100
Subject: [committed] mips.md macroisation (9/n)

Part 9 of the mips.md macroisation process.  This patch handles the
CP1 indexed load/store insns.  All such insns have a length of 4,
so we were working against ourselves by using mips_fetch_insns to
compute the default length.

Bootstrapped & regression tested on mips-sgi-irix6.5.  Applied to head.

Richard


	* config/mips/mips.md (length): Don't use mips_fetch_insns for indexed
	loads and stores.
	(*lwxc1_<mode>, *ldxc1_<mode>, *swxc1_<mode>, *sdxc1_<mode>): Name
	formerly unnamed patterns.  Redefine using :P for the address.  Remove
	explicit length attributes.

Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.279
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.279 mips.md
--- config/mips/mips.md	23 Aug 2004 08:11:40 -0000	1.279
+++ config/mips/mips.md	23 Aug 2004 08:13:24 -0000
@@ -181,9 +181,9 @@ (define_attr "length" ""
 
 	  (eq_attr "type" "const")
 	  (symbol_ref "mips_const_insns (operands[1]) * 4")
-	  (eq_attr "type" "load,fpload,fpidxload")
+	  (eq_attr "type" "load,fpload")
 	  (symbol_ref "mips_fetch_insns (operands[1]) * 4")
-	  (eq_attr "type" "store,fpstore,fpidxstore")
+	  (eq_attr "type" "store,fpstore")
 	  (symbol_ref "mips_fetch_insns (operands[0]) * 4")
 
 	  ;; In the worst case, a call macro will take 8 instructions:
@@ -3717,85 +3717,41 @@ (define_expand "reload_outcc"
 ;; these instructions can only be used to load and store floating
 ;; point registers, that would probably cause trouble in reload.
 
-(define_insn ""
+(define_insn "*lwxc1_<mode>"
   [(set (match_operand:SF 0 "register_operand" "=f")
-	(mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "register_operand" "d"))))]
+	(mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
+			(match_operand:P 2 "register_operand" "d"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
   "lwxc1\t%0,%1(%2)"
-  [(set_attr "type"	"fpidxload")
-   (set_attr "mode"	"SF")
-   (set_attr "length"   "4")])
-
-(define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d")
-			 (match_operand:DI 2 "register_operand" "d"))))]
-  "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
-  "lwxc1\t%0,%1(%2)"
-  [(set_attr "type"	"fpidxload")
-   (set_attr "mode"	"SF")
-   (set_attr "length"   "4")])
-
-(define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "register_operand" "d"))))]
-  "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "ldxc1\t%0,%1(%2)"
-  [(set_attr "type"	"fpidxload")
-   (set_attr "mode"	"DF")
-   (set_attr "length"   "4")])
+  [(set_attr "type" "fpidxload")
+   (set_attr "mode" "SF")])
 
-(define_insn ""
+(define_insn "*ldxc1_<mode>"
   [(set (match_operand:DF 0 "register_operand" "=f")
-	(mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d")
-			 (match_operand:DI 2 "register_operand" "d"))))]
+	(mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
+			(match_operand:P 2 "register_operand" "d"))))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
   "ldxc1\t%0,%1(%2)"
-  [(set_attr "type"	"fpidxload")
-   (set_attr "mode"	"DF")
-   (set_attr "length"   "4")])
-
-(define_insn ""
-  [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "register_operand" "d")))
-	(match_operand:SF 0 "register_operand" "f"))]
-  "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
-  "swxc1\t%0,%1(%2)"
-  [(set_attr "type"	"fpidxstore")
-   (set_attr "mode"	"SF")
-   (set_attr "length"   "4")])
+  [(set_attr "type" "fpidxload")
+   (set_attr "mode" "DF")])
 
-(define_insn ""
-  [(set (mem:SF (plus:DI (match_operand:DI 1 "register_operand" "d")
-			 (match_operand:DI 2 "register_operand" "d")))
+(define_insn "*swxc1_<mode>"
+  [(set (mem:SF (plus:P (match_operand:P 1 "register_operand" "d")
+			(match_operand:P 2 "register_operand" "d")))
 	(match_operand:SF 0 "register_operand" "f"))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT"
   "swxc1\t%0,%1(%2)"
-  [(set_attr "type"	"fpidxstore")
-   (set_attr "mode"	"SF")
-   (set_attr "length"   "4")])
-
-(define_insn ""
-  [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
-			 (match_operand:SI 2 "register_operand" "d")))
-	(match_operand:DF 0 "register_operand" "f"))]
-  "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
-  "sdxc1\t%0,%1(%2)"
-  [(set_attr "type"	"fpidxstore")
-   (set_attr "mode"	"DF")
-   (set_attr "length"   "4")])
+  [(set_attr "type" "fpidxstore")
+   (set_attr "mode" "SF")])
 
-(define_insn ""
-  [(set (mem:DF (plus:DI (match_operand:DI 1 "register_operand" "d")
-			 (match_operand:DI 2 "register_operand" "d")))
+(define_insn "*sdxc1_<mode>"
+  [(set (mem:DF (plus:P (match_operand:P 1 "register_operand" "d")
+			(match_operand:P 2 "register_operand" "d")))
 	(match_operand:DF 0 "register_operand" "f"))]
   "ISA_HAS_FP4 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
   "sdxc1\t%0,%1(%2)"
-  [(set_attr "type"	"fpidxstore")
-   (set_attr "mode"	"DF")
-   (set_attr "length"   "4")])
+  [(set_attr "type" "fpidxstore")
+   (set_attr "mode" "DF")])
 
 ;; 16-bit Integer moves

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