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Re: MIPS patch, for non-canonical conditional move patterns
On Sun, 2004-08-15 at 01:39, Richard Sandiford wrote:
> You're going to run into a few merge problems with mips.md though...
> Could I convince you to turn the testcase into a dejagnu one? ;)
Here is the patch I checked in. Updated to resolve the merge conflicts
with your define_predicates patch, and I added scan-assembler dejagnu
testcases. I am not sure about the usefulness of the testcases though,
as the compiler could choose to optimize differently turning e.g. movz
into movn. The scan-assembler support doesn't seem to have enough
intelligence to deal with cases like this. I had to split my testcase
into 3 just to avoid ambiguities in the scan-assembler tests.
--
Jim Wilson, GNU Tools Support, http://www.SpecifixInc.com
gcc/ChangeLog
2004-08-17 James E Wilson <wilson@specifixinc.com>
* config/mips/mips.c (gen_conditional_move): Use GET_MODE (op0) instead
of VOIDmode for comparison code mode.
* config/mips/mips.md: For conditional move patterns, use mode of
first compare operand for comparison mode, instead of VOIDmode.
gcc/testsuite/ChangeLog
2004-08-17 James E Wilson <wilson@specifixinc.com>
* gcc.dg/mips-movcc-1.c: New.
* gcc.dg/mips-movcc-2.c: New.
* gcc.dg/mips-movcc-3.c: New.
Index: mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.445
diff -p -r1.445 mips.c
*** mips.c 15 Aug 2004 15:45:11 -0000 1.445
--- mips.c 17 Aug 2004 04:42:38 -0000
*************** gen_conditional_move (rtx *operands)
*** 2578,2584 ****
mips_emit_compare (&code, &op0, &op1, true);
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
! gen_rtx_fmt_ee (code, VOIDmode,
op0, op1),
operands[2], operands[3])));
}
--- 2578,2585 ----
mips_emit_compare (&code, &op0, &op1, true);
emit_insn (gen_rtx_SET (VOIDmode, operands[0],
gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
! gen_rtx_fmt_ee (code,
! GET_MODE (op0),
op0, op1),
operands[2], operands[3])));
}
Index: mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.266
diff -p -r1.266 mips.md
*** mips.md 14 Aug 2004 20:55:56 -0000 1.266
--- mips.md 17 Aug 2004 04:42:41 -0000
*************** dsrl\t%3,%3,1\n\
*** 7310,7318 ****
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
--- 7310,7318 ----
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator:SI 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
*************** dsrl\t%3,%3,1\n\
*** 7325,7333 ****
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
--- 7325,7333 ----
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator:DI 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SI 2 "reg_or_0_operand" "dJ,0")
(match_operand:SI 3 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE"
*************** dsrl\t%3,%3,1\n\
*** 7340,7348 ****
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
--- 7340,7348 ----
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=d,d")
(if_then_else:SI
! (match_operator:CC 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
(match_operand:SI 1 "reg_or_0_operand" "dJ,0")
(match_operand:SI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7355,7363 ****
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
--- 7355,7363 ----
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator:SI 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
*************** dsrl\t%3,%3,1\n\
*** 7370,7378 ****
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
--- 7370,7378 ----
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator:DI 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DI 2 "reg_or_0_operand" "dJ,0")
(match_operand:DI 3 "reg_or_0_operand" "0,dJ")))]
"(ISA_HAS_CONDMOVE || ISA_HAS_INT_CONDMOVE) && TARGET_64BIT"
*************** dsrl\t%3,%3,1\n\
*** 7385,7393 ****
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
(match_operand:DI 1 "reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
--- 7385,7393 ----
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=d,d")
(if_then_else:DI
! (match_operator:CC 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
(match_operand:DI 1 "reg_or_0_operand" "dJ,0")
(match_operand:DI 2 "reg_or_0_operand" "0,dJ")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_64BIT"
*************** dsrl\t%3,%3,1\n\
*** 7400,7408 ****
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
--- 7400,7408 ----
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator:SI 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7415,7423 ****
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
--- 7415,7423 ----
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator:DI 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:SF 2 "register_operand" "f,0")
(match_operand:SF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7430,7438 ****
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
--- 7430,7438 ----
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=f,f")
(if_then_else:SF
! (match_operator:CC 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
(match_operand:SF 1 "register_operand" "f,0")
(match_operand:SF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7445,7453 ****
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
--- 7445,7453 ----
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator:SI 4 "equality_operator"
! [(match_operand:SI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7460,7468 ****
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
--- 7460,7468 ----
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator:DI 4 "equality_operator"
! [(match_operand:DI 1 "register_operand" "d,d")
! (const_int 0)])
(match_operand:DF 2 "register_operand" "f,0")
(match_operand:DF 3 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
*************** dsrl\t%3,%3,1\n\
*** 7475,7483 ****
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
--- 7475,7483 ----
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=f,f")
(if_then_else:DF
! (match_operator:CC 3 "equality_operator"
! [(match_operand:CC 4 "register_operand" "z,z")
! (const_int 0)])
(match_operand:DF 1 "register_operand" "f,0")
(match_operand:DF 2 "register_operand" "0,f")))]
"ISA_HAS_CONDMOVE && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
Index: gcc.dg/mips-movcc-1.c
===================================================================
RCS file: gcc.dg/mips-movcc-1.c
diff -N gcc.dg/mips-movcc-1.c
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gcc.dg/mips-movcc-1.c 17 Aug 2004 21:14:18 -0000
***************
*** 0 ****
--- 1,23 ----
+ /* { dg-do compile { target "mips*-*-*" } } */
+ /* { dg-options "-O2 -mips4" } */
+ /* { dg-final { scan-assembler "movz" } } */
+ /* { dg-final { scan-assembler "movn" } } */
+ /* { dg-final { scan-assembler "movt" } } */
+
+ int
+ sub1 (int i, int j, int k)
+ {
+ return k ? i : j;
+ }
+
+ int
+ sub2 (int i, int j, long l)
+ {
+ return !l ? i : j;
+ }
+
+ int
+ sub3 (int i, int j, float f)
+ {
+ return f ? i : j;
+ }
Index: gcc.dg/mips-movcc-2.c
===================================================================
RCS file: gcc.dg/mips-movcc-2.c
diff -N gcc.dg/mips-movcc-2.c
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gcc.dg/mips-movcc-2.c 17 Aug 2004 21:14:18 -0000
***************
*** 0 ****
--- 1,23 ----
+ /* { dg-do compile { target "mips*-*-*" } } */
+ /* { dg-options "-O2 -mips4" } */
+ /* { dg-final { scan-assembler "movz" } } */
+ /* { dg-final { scan-assembler "movn" } } */
+ /* { dg-final { scan-assembler "movf" } } */
+
+ long
+ sub4 (long i, long j, long k)
+ {
+ return k ? i : j;
+ }
+
+ long
+ sub5 (long i, long j, int k)
+ {
+ return !k ? i : j;
+ }
+
+ long
+ sub6 (long i, long j, float f)
+ {
+ return !f ? i : j;
+ }
Index: gcc.dg/mips-movcc-3.c
===================================================================
RCS file: gcc.dg/mips-movcc-3.c
diff -N gcc.dg/mips-movcc-3.c
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- gcc.dg/mips-movcc-3.c 17 Aug 2004 21:14:18 -0000
***************
*** 0 ****
--- 1,44 ----
+ /* { dg-do compile { target "mips*-*-*" } } */
+ /* { dg-options "-O2 -mips4" } */
+ /* { dg-final { scan-assembler "movz.s" } } */
+ /* { dg-final { scan-assembler "movn.s" } } */
+ /* { dg-final { scan-assembler "movt.s" } } */
+ /* { dg-final { scan-assembler "movz.d" } } */
+ /* { dg-final { scan-assembler "movn.d" } } */
+ /* { dg-final { scan-assembler "movf.d" } } */
+
+ float
+ sub7 (float f, float g, int i)
+ {
+ return i ? f : g;
+ }
+
+ float
+ sub8 (float f, float g, long l)
+ {
+ return !l ? f : g;
+ }
+
+ float
+ sub9 (float f, float g, float h)
+ {
+ return h ? f : g;
+ }
+
+ double
+ suba (double f, double g, int i)
+ {
+ return i ? f : g;
+ }
+
+ double
+ subb (double f, double g, long l)
+ {
+ return !l ? f : g;
+ }
+
+ double
+ subc (double f, double g, double h)
+ {
+ return !h ? f : g;
+ }