Re: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bittargets

[Nigel Stephens <nigel at mips dot com>]

Maciej W. Rozycki wrote:

> On Wed, 4 Aug 2004, Nigel Stephens wrote:
>
>  
>
> > > Here are my proposals I've referred to previously.  Instruction counts
> > > are 9, 9 and 10, respectively, as I've missed an additional instruction
> > > required to handle shifts by 0 (or actually any multiples of 64). 
> > >      
> > IMHO handling a shift by zero correctly is important.
> >    
>
> Agreed, hence an additional instruction needed.
>
>  
>
> > > 		"not	%1, %3\n\t"
> > > 		"srlv	%1, %L2, %1\n\t"
> > > 		"srl	%1, %1, 1\n\t"
> > >
> > >      
> > Why not the shorter:
> >
> >    
> >
> > > 		"neg	%1, %3\n\t"
> > > 		"srlv	%1, %L2, %1\n\t"
> > >      
>
> Notice the difference -- this shorter code doesn't handle shifts by zero
> correctly. ;-)
>  

Ah yes, I see. I did it with a conditional move to fix up after the 
shift, but same result.

> > And then in __ashrdi3:
> >
> > 		"andi	%1, %3, 0x20\n\t"
> > 		".set	push\n\t"
> > 		".set	noat\n\t"
> > 		"sra	$1, %M2, 31\n\t"
> > 		"movn	%L0, %M0, %1\n\t"
> > 		"movn	%M0, $1, %1\n\t"
> > 		".set	pop"
> >
> > Cute, but I think that should be
> >
> > 	"sra	$1, %M0, 31\n\t"
> >
> > (i.e %M0 not %M2)
> >    
>
> Well, I've tested it for all shift counts and it works properly as is --
> we care of the value of bit #31 to be shifted only and at this stage it's
> the same in both registers.  So it's just a matter of style.
>
>  

OK, I see

Nigel