VIA C3 cmov instruction patch

["Philipp Hasse" <dream-weaver at gmx dot net>]

Hi,

I'm new to this mailing list and I hope I hit the right one for my concern.
I have a VIA EPIA-M board with a C3 cpu on it and I did an intensive search
on the Internet to find which compiler flags to use.
According to VIA the C3 is a native i686 cpu without the cmov instruction
set. Due to the fact that gcc uses the cmov instructions when -march=i686 is
used  respectively if PROCESSOR_PENTIUMPRO is selected in the processor
alias table gcc will generate invalid instructions for the c3 (see
20000609-1.c in gcc-3.3.3/gcc/testsuite/gcc.dg and compile with -march=i686
only).
I wrote a little patch which will disable the cmov instructions
when -march=c3 is used.
For it I introduced a new variable named x86_cmove_mask which will mask out
the m_PPRO flag in TARGET_CMOVE.
I'm not that into compiler developement but maybe one of you could tell me
if the patch is pragmatically correct in the context of the gcc sources.

Philipp Hasse

diff -Nru gcc-3.3.3/gcc/config/i386/i386.c
gcc-3.3.3-patched/gcc/config/i386/i386.c
--- gcc-3.3.3/gcc/config/i386/i386.c    2004-02-06 20:43:30.000000000 +0100
+++ gcc-3.3.3-patched/gcc/config/i386/i386.c    2004-07-31
13:14:54.680116576 +0200
@@ -413,6 +413,7 @@
 const int x86_use_bit_test = m_386;
 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON | m_K6;
 const int x86_cmove = m_PPRO | m_ATHLON | m_PENT4;
+      int x86_cmove_mask = 0;
 const int x86_3dnow_a = m_ATHLON;
 const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON | m_PENT4;
 const int x86_branch_hints = m_PENT4;
@@ -981,7 +982,8 @@
       {"pentium-mmx", PROCESSOR_PENTIUM, PTA_MMX},
       {"winchip-c6", PROCESSOR_I486, PTA_MMX},
       {"winchip2", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
-      {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},
+/*      {"c3", PROCESSOR_I486, PTA_MMX | PTA_3DNOW},*/
+      {"c3", PROCESSOR_PENTIUMPRO, PTA_MMX | PTA_3DNOW},
       {"i686", PROCESSOR_PENTIUMPRO, 0},
       {"pentiumpro", PROCESSOR_PENTIUMPRO, 0},
       {"pentium2", PROCESSOR_PENTIUMPRO, PTA_MMX},
@@ -1111,7 +1113,16 @@

   if (i == pta_size)
     error ("bad value (%s) for -march= switch", ix86_arch_string);
-
+
+  /**
+   * This patch will enable i686 support for the VIA C3 processor by
masking out
+   *   m_PPRO in x86_cmove.
+   */
+  if (! strcmp ("c3", ix86_arch_string)) {
+    warning("-march=c3 selected: using i686 layout and disabling cmov
instructions!");
+    x86_cmove_mask = m_PPRO;
+  }
+
   for (i = 0; i < pta_size; i++)
     if (! strcmp (ix86_cpu_string, processor_alias_table[i].name))
       {
diff -Nru gcc-3.3.3/gcc/config/i386/i386.h
gcc-3.3.3-patched/gcc/config/i386/i386.h
--- gcc-3.3.3/gcc/config/i386/i386.h    2004-02-06 20:43:31.000000000 +0100
+++ gcc-3.3.3-patched/gcc/config/i386/i386.h    2004-07-31
13:15:34.216106192 +0200
@@ -224,6 +224,8 @@
 extern const int x86_arch_always_fancy_math_387, x86_shift1;
 extern int x86_prefetch_sse;

+extern int x86_cmove_mask;
+
 #define TARGET_USE_LEAVE (x86_use_leave & CPUMASK)
 #define TARGET_PUSH_MEMORY (x86_push_memory & CPUMASK)
 #define TARGET_ZERO_EXTEND_WITH_AND (x86_zero_extend_with_and & CPUMASK)
@@ -231,7 +233,8 @@
 #define TARGET_UNROLL_STRLEN (x86_unroll_strlen & CPUMASK)
 /* For sane SSE instruction set generation we need fcomi instruction.  It
is
    safe to enable all CMOVE instructions.  */
-#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
+/*#define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)*/
+#define TARGET_CMOVE (((x86_cmove & ~x86_cmove_mask) & (1 << ix86_arch)) ||
TARGET_SSE)
 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & CPUMASK)
 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & CPUMASK)
 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & CPUMASK)