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Re: [RFA/RFT] Tree-level lowering of generic vectors, part 3

I'm delighted to see the vector modes out of machmode.def, but I gotta
ask - how did you derive the list of CPUs with vector hardware, and
the set of modes relevant to each CPU?  I know there are other CPUs
supported by GCC that have vector instructions, although their machine
descriptions may not currently be taking advantage of them (and it
doesn't make sense to define the modes until they do).

zw
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