frv: asm reloads for pseudos assigned to memory fail

[Alexandre Oliva <aoliva at redhat dot com>]

I got big, ugly piece of C code the other day that passed to an asm
statement a variable of type int, that had been previously assigned
the value of a 64-bit variable.

Turned out the asm ended up with subreg for the 64-bit variable, that
hadn't changed, and the corresponding pseudo ended up assigned to a
stack slot.

Reload emitted the input reload, and then immediately attempted to
recognize the emitted instruction, which it does for all reloads for
asms.  Unfortunately, the insn was recognized as movsi_internal, but
it failed strict constraint checking because we had a pseudo, and the
insn doesn't accept memory operands.

Even if I relaxed the check to be non-strict (since the next round of
reloading would presumably fix things up, I thought), it failed
because the pseudo had become a mem(fp+offset), but the insn had
already been recognized as one that doesn't accept memory inputs, so
it just fell apart.

The work around I came up with was to enable the pattern to accept
memory inputs that fit without reloading, such that it doesn't end up
loading constants from memory (the reason why the memory loads were
split into a separate insn).  I'm hoping this won't prevent mems from
matching whose addresses require reloading (e.g., an fp offset that is
too big to fit the immediate offset of a load instruction).

Tested on i686-pc-linux-gnu-x-frv-elf, along with another patch
needed for target libraries to build
<URL:http://gcc.gnu.org/ml/gcc-patches/2004-05/msg01795.html>.

Ok to install both?

Index: gcc/ChangeLog
from  Alexandre Oliva  <aoliva@redhat.com>

	* config/frv/frv.md (movqi_internal, movhi_internal,
	movsi_internal): Add backup alternatives for memory inputs.

Index: gcc/config/frv/frv.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/frv/frv.md,v
retrieving revision 1.16
diff -u -p -r1.16 frv.md
--- gcc/config/frv/frv.md 7 Jul 2004 19:24:12 -0000 1.16
+++ gcc/config/frv/frv.md 16 Jul 2004 18:51:03 -0000
@@ -1312,12 +1312,12 @@
    (set_attr "type" "gload,fload")])
 
 (define_insn "*movqi_internal"
-  [(set (match_operand:QI 0 "move_destination_operand" "=d,d,m,m,?f,?f,?d,?m,f")
-	(match_operand:QI 1 "move_source_operand"       "L,d,d,O, d, f, f, f,GO"))]
+  [(set (match_operand:QI 0 "move_destination_operand" "=d,d,m,m,?f,?f,?d,?m,f,d,f")
+	(match_operand:QI 1 "move_source_operand"       "L,d,d,O, d, f, f, f,GO,!m,!m"))]
   "register_operand(operands[0], QImode) || reg_or_0_operand (operands[1], QImode)"
   "* return output_move_single (operands, insn);"
   [(set_attr "length" "4")
-   (set_attr "type" "int,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf")])
+   (set_attr "type" "int,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "general_operand" "")
@@ -1341,12 +1341,12 @@
    (set_attr "type" "gload,fload")])
 
 (define_insn "*movhi_internal"
-  [(set (match_operand:HI 0 "move_destination_operand" "=d,d,d,m,m,?f,?f,?d,?m,f")
-	(match_operand:HI 1 "move_source_operand"       "L,n,d,d,O, d, f, f, f,GO"))]
+  [(set (match_operand:HI 0 "move_destination_operand" "=d,d,d,m,m,?f,?f,?d,?m,f,d,f")
+	(match_operand:HI 1 "move_source_operand"       "L,n,d,d,O, d, f, f, f,GO,!m,!m"))]
   "register_operand(operands[0], HImode) || reg_or_0_operand (operands[1], HImode)"
   "* return output_move_single (operands, insn);"
-  [(set_attr "length" "4,8,4,4,4,4,4,4,4,4")
-   (set_attr "type" "int,multi,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf")])
+  [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4")
+   (set_attr "type" "int,multi,int,gstore,gstore,movgf,fsconv,movfg,fstore,movgf,gload,fload")])
 
 ;; Split 2 word load of constants into sethi/setlo instructions
 (define_split
@@ -1402,6 +1402,14 @@
 ;; The resulting sequences for loading constants into FPRs are preferable
 ;; even when we're not generating PIC code.
 
+;; However, if we don't accept input from memory at all in the generic
+;; movsi pattern, reloads for asm instructions that reference pseudos
+;; that end up assigned to memory will fail to match, because we
+;; recognize them right after they're emitted, and we don't
+;; re-recognize them again after the substitution for memory.  So keep
+;; a memory constraint available, just make sure reload won't be
+;; tempted to use it.
+
 (define_insn "*movsi_load"
   [(set (match_operand:SI 0 "register_operand" "=d,f")
 	(match_operand:SI 1 "frv_load_operand" "m,m"))]
@@ -1436,12 +1444,12 @@
    (set_attr "length" "4")])
 
 (define_insn "*movsi_internal"
-  [(set (match_operand:SI 0 "move_destination_operand" "=d,d,d,m,m,z,d,d,f,f,m,?f,?z")
-	(match_operand:SI 1 "move_source_operand"      "L,n,d,d,O,d,z,f,d,f,f,GO,GO"))]
+  [(set (match_operand:SI 0 "move_destination_operand" "=d,d,d,m,m,z,d,d,f,f,m,?f,?z,d,f")
+	(match_operand:SI 1 "move_source_operand"      "L,n,d,d,O,d,z,f,d,f,f,GO,GO,!m,!m"))]
   "register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode)"
   "* return output_move_single (operands, insn);"
-  [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4,4")
-   (set_attr "type" "int,multi,int,gstore,gstore,spr,spr,movfg,movgf,fsconv,fstore,movgf,spr")])
+  [(set_attr "length" "4,8,4,4,4,4,4,4,4,4,4,4,4,4,4")
+   (set_attr "type" "int,multi,int,gstore,gstore,spr,spr,movfg,movgf,fsconv,fstore,movgf,spr,gload,fload")])
 
 ;; Split 2 word load of constants into sethi/setlo instructions
 (define_insn_and_split "*movsi_2word"


-- 
Alexandre Oliva             http://www.ic.unicamp.br/~oliva/
Red Hat Compiler Engineer   aoliva@{redhat.com, gcc.gnu.org}
Free Software Evangelist  oliva@{lsd.ic.unicamp.br, gnu.org}