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Re: x86: CPU type requirements incorrect for various vector mode operations


On Thu, Jul 08, 2004 at 03:25:22PM +0200, Jan Beulich wrote:
> 	(movv2sf_internal): Allow beginning with MMX.
> 	(movv2df_internal, movv8hi_internal, movv16qi_internal): Allow
> 	beginning with SSE and use SSE instruction when SSE2 unavailable.
> 	(movv2df, movv8hi, movv16qi, pushv2di, pushv8hi, pushv16qi, pushv4si):
> 	Allow beginning with SSE.
> 	(movv2sf, pushv2sf): Allow beginning with MMX.

What's the logic here?


> +/* Extracts one of the four words of A.  The selector N must be immediate.*/
> +#if 0
> +static __inline int
> +_mm_extract_pi16 (__m64 __A, int __N)
> +{
> +  return __builtin_ia32_pextrw ((__v4hi)__A, __N);
> +}
> +
> +static __inline int
> +_m_pextrw (__m64 __A, int __N)
> +{
> +  return _mm_extract_pi16 (__A, __N);
> +}
> +#else
> +#define _mm_extract_pi16(A, N) \
> +  __builtin_ia32_pextrw ((__v4hi)(A), (N))
> +#define _m_pextrw(A, N)		_mm_extract_pi16((A), (N))
> +#endif

These should be written

static __inline int __attribute__((__always_inline__))
_mm_extract_pi16 (__m64 const __A, int const __N)
{
  return __builtin_ia32_pextrw ((__v4hi)__A, __N);
}

That should propagate the constant to the builtin even at -O0.



r~


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