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[arm] Fix maverick load pool range
- From: Paul Brook <paul at codesourcery dot com>
- To: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Cc: Richard Earnshaw <rearnsha at arm dot com>
- Date: Wed, 30 Jun 2004 16:47:54 +0100
- Subject: [arm] Fix maverick load pool range
- Organization: CodeSourcery
The current instruction patterns don't allow loading constants into
coprocessor regs. However these can be produced indirectly by reload.
The attached patch below sets the pool range and allows constants for maverick
coprocessor load instructions. This fixes an ICE discovered while building
libgcc.
Ok?
Paul
2004-06-30 Paul Brook <paul@codesourcery.com>
* config/arm/cirrus.md (cirrus_arm_movdi, cirrus_movsf_hard_insn,
cirrus_movdf_hard_insn): Set pool ranges for coprocessor loads.
Index: config/arm/cirrus.md
===================================================================
RCS file: /var/cvsroot/gcc-cvs/gcc/gcc/config/arm/cirrus.md,v
retrieving revision 1.7
diff -u -p -r1.7 cirrus.md
--- config/arm/cirrus.md 4 Feb 2004 19:15:23 -0000 1.7
+++ config/arm/cirrus.md 30 Jun 2004 15:40:36 -0000
@@ -370,7 +370,7 @@
(define_insn "*cirrus_arm_movdi"
[(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v")
- (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,m,v,v"))]
+ (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,mi,v,v"))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK"
"*
{
@@ -395,8 +395,8 @@
}"
[(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4")
(set_attr "type" " *,load2,store2, *, *, load2,store2, *")
- (set_attr "pool_range" " *,1020, *, *, *, *, *, *")
- (set_attr "neg_pool_range" " *,1012, *, *, *, *, *, *")
+ (set_attr "pool_range" " *,1020, *, *, *, 1020, *, *")
+ (set_attr "neg_pool_range" " *,1012, *, *, *, 1008, *, *")
(set_attr "cirrus" "not, not, not,move,normal,double,double,normal")]
)
@@ -427,7 +427,7 @@
(define_insn "*cirrus_movsf_hard_insn"
[(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
- (match_operand:SF 1 "general_operand" "v,m,r,v,v,r,mE,r"))]
+ (match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]
"TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK
&& (GET_CODE (operands[0]) != MEM
|| register_operand (operands[1], SFmode))"
@@ -442,14 +442,14 @@
str%?\\t%1, %0\\t%@ float"
[(set_attr "length" " *, *, *, *, *, 4, 4, 4")
(set_attr "type" " *, load1, *, *,store1, *,load1,store1")
- (set_attr "pool_range" " *, *, *, *, *, *,4096, *")
- (set_attr "neg_pool_range" " *, *, *, *, *, *,4084, *")
+ (set_attr "pool_range" " *, 1020, *, *, *, *,4096, *")
+ (set_attr "neg_pool_range" " *, 1008, *, *, *, *,4084, *")
(set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")]
)
(define_insn "*cirrus_movdf_hard_insn"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m")
- (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,m,r,v,v"))]
+ (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,mF,r,v,v"))]
"TARGET_ARM
&& TARGET_HARD_FLOAT && TARGET_MAVERICK
&& (GET_CODE (operands[0]) != MEM
@@ -471,8 +471,8 @@
}"
[(set_attr "type" "load1,store2, *,store2,load1, *, load1, *, *,store2")
(set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4")
- (set_attr "pool_range" " *, *, *, *, 252, *, *, *, *, *")
- (set_attr "neg_pool_range" " *, *, *, *, 244, *, *, *, *, *")
+ (set_attr "pool_range" " *, *, *, *, 252, *, 1020, *, *, *")
+ (set_attr "neg_pool_range" " *, *, *, *, 244, *, 1008, *, *, *")
(set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")]
)