Re: [arm] Fix invalid store instructions

[Paul Brook <paul at codesourcery dot com>]

> My feeling is that this is an MI bug not a target specific one, so I
> think it should really be fixed in the mid-end.
>
> There is no way of representing an early-clobber type behaviour in the
> constraints for a memory operand with pre/post operations so the
> compiler really must assume that it does happen and prevent any further
> use of the base register in the insn.

FWIW We also encounter similar issues with base+index load-double 
instructions, even when base value writeback is not specified. These are much 
easier to reproduce, eg.
long long foo(char *p, int n){return *(long long *)(p+n);}
Without hacks in the doubleword assembly output routines this would compile to

foo:
  ldrd r0, [r0, r1] @illegal because destination {r0-r1} overlaps index {r1}
  bx lr

> It's unclear to me at this time whether this has always been a
> theoretical problem with the compiler, or if it's something new that's
> been introduced by the tree-ssa changes.  I'm not aware that we suffered
> from this problem before those changes were merged.

The problem is still present, just harder to reproduce.
The example I gave generates invalid code with compilers from csl-arm-branch 
(3.4 based) and 3.3.2.

Paul