This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Removing DEBUG_G_MODE from the MIPS port
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: echristo at redhat dot com
- Date: Sun, 16 May 2004 09:45:27 +0100
- Subject: Removing DEBUG_G_MODE from the MIPS port
mips.md has lots of code to handle 64-bit operations on 32-bit targets.
By and large, this code doesn't do anything special; it just implements
the same kind of sequences the optabs.c would use.
I guess the idea was originally to have gradual lowering. 64-bit operations
would be kept together at first, making it easier for the rtl optimisers to
handle them. We'd then split them after reload in order to give the later
optimisers chance to operate on the individual instructions.
However, now that we have tree-ssa, this all seems less worthwhile.
Many of the optimisations that would benefit from atomic operations are
done at the tree level instead. And if we split the operations at rtl
expansion time, the rtl optimisers will have more chance to simplify
the individual instructions.
The patch below therefore gets rid of this code (which was controlled by
TARGET_DEBUG_G_MODE). I benchmarked the effect on a VR5500A board with
both "-mabi=eabi -mgp32" and "-mabi=eabi -mgp32 -mlong64", the latter
giving more scope for 64-bit operations. There was no measurable
difference in performance.
The patch does however seem to be a significant size win. I compared
the c-torture before and after the patch (using the same two option sets)
and got the following:
-mlong32: 52 files changed, 2663 insertions(+), 2949 deletions(-)
-mlong64: 106 files changed, 6880 insertions(+), 7558 deletions(-)
As I mentioned above, I think this is mostly due to the heavy-duty
rtl optimisers being able to operate on individual instructions.
One effect of this patch is that we now use __ashldi3, __ashrdi3 and
__lshrdi3 for shifts by variable amounts. The existing inline versions
are quite big though, so this should at least be a size win in many cases.
Tested on mips64vrel-elf. Also bootstrapped & regression tested on
mips-sgi-irix6.5 (but before the tree-ssa merge). Eric, is this
OK with you?
Richard
* config/mips/mips.h (MASK_DEBUG_G, TARGET_DEBUG_G_MODE): Delete.
(TARGET_SWITCHES): Remove debugg.
* config/mips/mips.md (adddi3, ashldi3, ashrdi3, lshrdi3): Only handle
TARGET_64BIT.
(subdi3): Replace the define_expand with a define_insn, the latter
renamed from subdi3_internal_3.
(negdi2): Likewise negdi2_internal_2.
(adddi3_internal_[12], subdi3_internal, ashldi3_internal{,2,3},
ashrdi3_internal{,2,3}, lshrdi3_internal{,2,3}): Remove patterns
and associated define_splits.
(adddi3_internal): Renamed from adddi3_internal_3.
(ashldi3_internal): Likewise ashldi3_internal4.
(ashrdi3_internal): Likewise ashrdi3_internal4.
(lshrdi3_internal): Likewise lshrdi3_internal4.
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.341
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.341 mips.h
--- config/mips/mips.h 7 May 2004 15:06:15 -0000 1.341
+++ config/mips/mips.h 16 May 2004 07:20:18 -0000
@@ -178,7 +178,6 @@ #define MASK_FP_EXCEPTIONS 0x10000000
#define MASK_DEBUG 0 /* unused */
#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
#define MASK_DEBUG_D 0 /* don't do define_split's */
-#define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
/* Dummy switches used only in specs */
#define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
@@ -200,7 +199,6 @@ #define TARGET_MIPS_AS (!TARGET_GAS)
#define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
#define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
#define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
-#define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
/* Reg. Naming in .s ($21 vs. $a0) */
#define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
@@ -677,8 +675,6 @@ #define TARGET_SWITCHES \
{"debugc", MASK_DEBUG_C, \
NULL}, \
{"debugd", MASK_DEBUG_D, \
- NULL}, \
- {"debugg", MASK_DEBUG_G, \
NULL}, \
{"", (TARGET_DEFAULT \
| TARGET_CPU_DEFAULT \
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.243
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.243 mips.md
--- config/mips/mips.md 10 May 2004 18:35:43 -0000 1.243
+++ config/mips/mips.md 16 May 2004 07:20:19 -0000
@@ -890,11 +890,10 @@ (define_split
})
(define_expand "adddi3"
- [(parallel [(set (match_operand:DI 0 "register_operand")
- (plus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "arith_operand")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+ [(set (match_operand:DI 0 "register_operand")
+ (plus:DI (match_operand:DI 1 "register_operand")
+ (match_operand:DI 2 "arith_operand")))]
+ "TARGET_64BIT"
{
/* If a large stack adjustment was forced into a register, we may be
asked to generate rtx such as:
@@ -916,156 +915,9 @@ (define_expand "adddi3"
emit_move_insn (operands[0], tmp);
DONE;
}
-
- if (TARGET_64BIT)
- {
- emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
})
-(define_insn "adddi3_internal_1"
- [(set (match_operand:DI 0 "register_operand" "=d,&d")
- (plus:DI (match_operand:DI 1 "register_operand" "0,d")
- (match_operand:DI 2 "register_operand" "d,d")))
- (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
-{
- return (REGNO (operands[0]) == REGNO (operands[1])
- && REGNO (operands[0]) == REGNO (operands[2]))
- ? "srl\t%3,%L0,31\;sll\t%M0,%M0,1\;sll\t%L0,%L1,1\;addu\t%M0,%M0,%3"
- : "addu\t%L0,%L1,%L2\;sltu\t%3,%L0,%L2\;addu\t%M0,%M1,%M2\;addu\t%M0,%M0,%3";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (plus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
- && (REGNO (operands[0]) != REGNO (operands[1])
- || REGNO (operands[0]) != REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))]
- "")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (plus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
- && (REGNO (operands[0]) != REGNO (operands[1])
- || REGNO (operands[0]) != REGNO (operands[2]))"
-
- [(set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))]
- "")
-
-(define_insn "adddi3_internal_2"
- [(set (match_operand:DI 0 "register_operand" "=d,d,d")
- (plus:DI (match_operand:DI 1 "register_operand" "%d,d,d")
- (match_operand:DI 2 "small_int" "P,J,N")))
- (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "@
- addu\t%L0,%L1,%2\;sltu\t%3,%L0,%2\;addu\t%M0,%M1,%3
- move\t%L0,%L1\;move\t%M0,%M1
- subu\t%L0,%L1,%n2\;sltu\t%3,%L0,%2\;subu\t%M0,%M1,1\;addu\t%M0,%M0,%3"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "12,8,16")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (plus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && INTVAL (operands[2]) > 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 0)
- (match_dup 2)))
-
- (set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (match_dup 3)))]
- "")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (plus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && INTVAL (operands[2]) > 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (plus:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 0) 4)
- (match_dup 2)))
-
- (set (subreg:SI (match_dup 0) 0)
- (plus:SI (subreg:SI (match_dup 1) 0)
- (match_dup 3)))]
- "")
-
-(define_insn "adddi3_internal_3"
+(define_insn "adddi3_internal"
[(set (match_operand:DI 0 "register_operand" "=d,d")
(plus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ,dJ")
(match_operand:DI 2 "arith_operand" "d,Q")))]
@@ -1281,91 +1133,7 @@ (define_insn "subsi3_internal"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
-(define_expand "subdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand")
- (minus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
-{
- if (TARGET_64BIT)
- {
- emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
- operands[2]));
- DONE;
- }
-
- operands[3] = gen_reg_rtx (SImode);
-})
-
-(define_insn "subdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (minus:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "sltu\t%3,%L1,%L2\;subu\t%L0,%L1,%L2\;subu\t%M0,%M1,%M2\;subu\t%M0,%M0,%3"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (minus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
- [(set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))]
- "")
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (minus:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
- && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
-
- [(set (match_dup 3)
- (ltu:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (minus:SI (subreg:SI (match_dup 1) 4)
- (subreg:SI (match_dup 2) 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 1) 0)
- (subreg:SI (match_dup 2) 0)))
-
- (set (subreg:SI (match_dup 0) 0)
- (minus:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))]
- "")
-
-(define_insn "subdi3_internal_3"
+(define_insn "subdi3"
[(set (match_operand:DI 0 "register_operand" "=d")
(minus:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:DI 2 "register_operand" "d")))]
@@ -2987,32 +2755,7 @@ (define_insn "negsi2"
[(set_attr "type" "arith")
(set_attr "mode" "SI")])
-(define_expand "negdi2"
- [(parallel [(set (match_operand:DI 0 "register_operand")
- (neg:DI (match_operand:DI 1 "register_operand")))
- (clobber (match_dup 2))])]
- "(TARGET_64BIT || !TARGET_DEBUG_G_MODE) && !TARGET_MIPS16"
-{
- if (TARGET_64BIT)
- {
- emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
- DONE;
- }
-
- operands[2] = gen_reg_rtx (SImode);
-})
-
-(define_insn "negdi2_internal"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (neg:DI (match_operand:DI 1 "register_operand" "d")))
- (clobber (match_operand:SI 2 "register_operand" "=d"))]
- "! TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "subu\t%L0,%.,%L1\;subu\t%M0,%.,%M1\;sltu\t%2,%.,%L0\;subu\t%M0,%M0,%2"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-(define_insn "negdi2_internal_2"
+(define_insn "negdi2"
[(set (match_operand:DI 0 "register_operand" "=d")
(neg:DI (match_operand:DI 1 "register_operand" "d")))]
"TARGET_64BIT && !TARGET_MIPS16"
@@ -5536,213 +5279,37 @@ (define_split
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "ashldi3"
- [(parallel [(set (match_operand:DI 0 "register_operand")
- (ashift:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+ [(set (match_operand:DI 0 "register_operand")
+ (ashift:DI (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ "TARGET_64BIT"
{
- if (TARGET_64BIT)
+ /* On the mips16, a shift of more than 8 is a four byte
+ instruction, so, for a shift between 8 and 16, it is just as
+ fast to do two shifts of 8 or less. If there is a lot of
+ shifting going on, we may win in CSE. Otherwise combine will
+ put the shifts back together again. This can be called by
+ function_arg, so we must be careful not to allocate a new
+ register if we've reached the reload pass. */
+ if (TARGET_MIPS16
+ && optimize
+ && GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) > 8
+ && INTVAL (operands[2]) <= 16
+ && ! reload_in_progress
+ && ! reload_completed)
{
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. This can be called by
- function_arg, so we must be careful not to allocate a new
- register if we've reached the reload pass. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16
- && ! reload_in_progress
- && ! reload_completed)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_ashldi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashldi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
+ rtx temp = gen_reg_rtx (DImode);
- emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
- operands[2]));
+ emit_insn (gen_ashldi3_internal (temp, operands[1], GEN_INT (8)));
+ emit_insn (gen_ashldi3_internal (operands[0], temp,
+ GEN_INT (INTVAL (operands[2]) - 8)));
DONE;
}
-
- operands[3] = gen_reg_rtx (SImode);
})
(define_insn "ashldi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "sll\t%3,%2,26\;\
-bgez\t%3,1f%#\;\
-sll\t%M0,%L1,%2\;\
-%(b\t3f\;\
-move\t%L0,%.%)\
-\n\n\
-%~1:\;\
-%(beq\t%3,%.,2f\;\
-sll\t%M0,%M1,%2%)\
-\n\;\
-subu\t%3,%.,%2\;\
-srl\t%3,%L1,%3\;\
-or\t%M0,%M0,%3\n\
-%~2:\;\
-sll\t%L0,%L1,%2\n\
-%~3:"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "48")])
-
-
-(define_insn "ashldi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 32) != 0"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "sll\t%M0,%L1,%2\;move\t%L0,%.";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashift:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashift:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashldi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashift:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return "sll\t%M0,%M1,%2\;srl\t%3,%L1,%4\;or\t%M0,%M0,%3\;sll\t%L0,%L1,%2";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashift:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashift:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_insn "ashldi3_internal4"
[(set (match_operand:DI 0 "register_operand" "=d")
(ashift:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))]
@@ -5872,208 +5439,33 @@ (define_split
{ operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
(define_expand "ashrdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand")
- (ashiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+ [(set (match_operand:DI 0 "register_operand")
+ (ashiftrt:DI (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ "TARGET_64BIT"
{
- if (TARGET_64BIT)
+ /* On the mips16, a shift of more than 8 is a four byte
+ instruction, so, for a shift between 8 and 16, it is just as
+ fast to do two shifts of 8 or less. If there is a lot of
+ shifting going on, we may win in CSE. Otherwise combine will
+ put the shifts back together again. */
+ if (TARGET_MIPS16
+ && optimize
+ && GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) > 8
+ && INTVAL (operands[2]) <= 16)
{
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_ashrdi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_ashrdi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
+ rtx temp = gen_reg_rtx (DImode);
- emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
- operands[2]));
+ emit_insn (gen_ashrdi3_internal (temp, operands[1], GEN_INT (8)));
+ emit_insn (gen_ashrdi3_internal (operands[0], temp,
+ GEN_INT (INTVAL (operands[2]) - 8)));
DONE;
}
-
- operands[3] = gen_reg_rtx (SImode);
})
(define_insn "ashrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "sll\t%3,%2,26\;\
-bgez\t%3,1f%#\;\
-sra\t%L0,%M1,%2\;\
-%(b\t3f\;\
-sra\t%M0,%M1,31%)\
-\n\n\
-%~1:\;\
-%(beq\t%3,%.,2f\;\
-srl\t%L0,%L1,%2%)\
-\n\;\
-subu\t%3,%.,%2\;\
-sll\t%3,%M1,%3\;\
-or\t%L0,%L0,%3\n\
-%~2:\;\
-sra\t%M0,%M1,%2\n\
-%~3:"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "48")])
-
-
-(define_insn "ashrdi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "sra\t%L0,%M1,%2\;sra\t%M0,%M1,31";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 4) (const_int 31)))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "ashrdi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;sra\t%M0,%M1,%2";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ashiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ashiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ashiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_insn "ashrdi3_internal4"
[(set (match_operand:DI 0 "register_operand" "=d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))]
@@ -6222,209 +5614,33 @@ (define_insn_and_split ""
(set_attr "length" "16")])
(define_expand "lshrdi3"
- [(parallel [(set (match_operand:DI 0 "register_operand")
- (lshiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))
- (clobber (match_dup 3))])]
- "TARGET_64BIT || (!TARGET_DEBUG_G_MODE && !TARGET_MIPS16)"
+ [(set (match_operand:DI 0 "register_operand")
+ (lshiftrt:DI (match_operand:DI 1 "register_operand")
+ (match_operand:SI 2 "arith_operand")))]
+ "TARGET_64BIT"
{
- if (TARGET_64BIT)
+ /* On the mips16, a shift of more than 8 is a four byte
+ instruction, so, for a shift between 8 and 16, it is just as
+ fast to do two shifts of 8 or less. If there is a lot of
+ shifting going on, we may win in CSE. Otherwise combine will
+ put the shifts back together again. */
+ if (TARGET_MIPS16
+ && optimize
+ && GET_CODE (operands[2]) == CONST_INT
+ && INTVAL (operands[2]) > 8
+ && INTVAL (operands[2]) <= 16)
{
- /* On the mips16, a shift of more than 8 is a four byte
- instruction, so, for a shift between 8 and 16, it is just as
- fast to do two shifts of 8 or less. If there is a lot of
- shifting going on, we may win in CSE. Otherwise combine will
- put the shifts back together again. */
- if (TARGET_MIPS16
- && optimize
- && GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- rtx temp = gen_reg_rtx (DImode);
-
- emit_insn (gen_lshrdi3_internal4 (temp, operands[1], GEN_INT (8)));
- emit_insn (gen_lshrdi3_internal4 (operands[0], temp,
- GEN_INT (INTVAL (operands[2]) - 8)));
- DONE;
- }
+ rtx temp = gen_reg_rtx (DImode);
- emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
- operands[2]));
+ emit_insn (gen_lshrdi3_internal (temp, operands[1], GEN_INT (8)));
+ emit_insn (gen_lshrdi3_internal (operands[0], temp,
+ GEN_INT (INTVAL (operands[2]) - 8)));
DONE;
}
-
- operands[3] = gen_reg_rtx (SImode);
})
(define_insn "lshrdi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=&d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16"
- "sll\t%3,%2,26\;\
-bgez\t%3,1f%#\;\
-srl\t%L0,%M1,%2\;\
-%(b\t3f\;\
-move\t%M0,%.%)\
-\n\n\
-%~1:\;\
-%(beq\t%3,%.,2f\;\
-srl\t%L0,%L1,%2%)\
-\n\;\
-subu\t%3,%.,%2\;\
-sll\t%3,%M1,%3\;\
-or\t%L0,%L0,%3\n\
-%~2:\;\
-srl\t%M0,%M1,%2\n\
-%~3:"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "48")])
-
-
-(define_insn "lshrdi3_internal2"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 32) != 0"
-{
- operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
- return "srl\t%L0,%M1,%2\;move\t%M0,%.";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (lshiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 4) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 4) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (lshiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 32) != 0"
-
- [(set (subreg:SI (match_dup 0) 4) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
- (set (subreg:SI (match_dup 0) 0) (const_int 0))]
-
- "operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);")
-
-
-(define_insn "lshrdi3_internal3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:SI 2 "small_int" "IJK")))
- (clobber (match_operand:SI 3 "register_operand" "=d"))]
- "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-{
- int amount = INTVAL (operands[2]);
-
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-
- return "srl\t%L0,%L1,%2\;sll\t%3,%M1,%4\;or\t%L0,%L0,%3\;srl\t%M0,%M1,%2";
-}
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "16")])
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (lshiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 4)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 0)
- (ior:SI (subreg:SI (match_dup 0) 0)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (lshiftrt:DI (match_operand:DI 1 "register_operand")
- (match_operand:SI 2 "small_int")))
- (clobber (match_operand:SI 3 "register_operand"))]
- "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT
- && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
- && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
- && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
- && (INTVAL (operands[2]) & 63) < 32
- && (INTVAL (operands[2]) & 63) != 0"
-
- [(set (subreg:SI (match_dup 0) 4)
- (lshiftrt:SI (subreg:SI (match_dup 1) 4)
- (match_dup 2)))
-
- (set (match_dup 3)
- (ashift:SI (subreg:SI (match_dup 1) 0)
- (match_dup 4)))
-
- (set (subreg:SI (match_dup 0) 4)
- (ior:SI (subreg:SI (match_dup 0) 4)
- (match_dup 3)))
-
- (set (subreg:SI (match_dup 0) 0)
- (lshiftrt:SI (subreg:SI (match_dup 1) 0)
- (match_dup 2)))]
-{
- int amount = INTVAL (operands[2]);
- operands[2] = GEN_INT (amount & 31);
- operands[4] = GEN_INT ((-amount) & 31);
-})
-
-
-(define_insn "lshrdi3_internal4"
[(set (match_operand:DI 0 "register_operand" "=d")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "arith_operand" "dI")))]