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[PATCH] Allow ColdFire register offset addressing
- From: Peter Barada <peter at the-baradas dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: peter at the-baradas dot com
- Date: Wed, 5 May 2004 09:55:12 -0400 (EDT)
- Subject: [PATCH] Allow ColdFire register offset addressing
ColdFire allows for register offset addressing to be *both* the source
and destination of a move.
2004-05-05 Peter Barada <peter@the-baradas.com>
* gcc/config/m68k/m68k.h(EXTRA_CONSTRAINT): add 'U' for
register offset addressing.
* gcc/config/m68k/m68k.md: Add 'U,U' alternative to ColdFire
variants of movsi,movhi,movqi insn patterns.
Index: m68k.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/m68k/m68k.md,v
retrieving revision 1.75
diff -c -3 -p -r1.75 m68k.md
*** m68k.md 16 Mar 2004 03:54:33 -0000 1.75
--- m68k.md 5 May 2004 13:48:27 -0000
***************
*** 676,683 ****
})
(define_insn ""
! [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g")
! (match_operand:SI 1 "general_operand" "g,r<Q>"))]
"TARGET_COLDFIRE"
"* return output_move_simode (operands);")
--- 676,683 ----
})
(define_insn ""
! [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
! (match_operand:SI 1 "general_operand" "g,r<Q>,U"))]
"TARGET_COLDFIRE"
"* return output_move_simode (operands);")
***************
*** 706,713 ****
"* return output_move_himode (operands);")
(define_insn ""
! [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g")
! (match_operand:HI 1 "general_operand" "g,r<Q>"))]
"TARGET_COLDFIRE"
"* return output_move_himode (operands);")
--- 706,713 ----
"* return output_move_himode (operands);")
(define_insn ""
! [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U")
! (match_operand:HI 1 "general_operand" "g,r<Q>,U"))]
"TARGET_COLDFIRE"
"* return output_move_himode (operands);")
***************
*** 742,749 ****
"* return output_move_qimode (operands);")
(define_insn ""
! [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,d*a")
! (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,di*a"))]
"TARGET_COLDFIRE"
"* return output_move_qimode (operands);")
--- 742,749 ----
"* return output_move_qimode (operands);")
(define_insn ""
! [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a")
! (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))]
"TARGET_COLDFIRE"
"* return output_move_qimode (operands);")
Index: m68k.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/m68k/m68k.h,v
retrieving revision 1.110
diff -c -3 -p -r1.110 m68k.h
*** m68k.h 10 Mar 2004 05:07:45 -0000 1.110
--- m68k.h 5 May 2004 13:48:28 -0000
*************** extern enum reg_class regno_reg_class[];
*** 735,741 ****
`Q' means address register indirect addressing mode.
`S' is for operands that satisfy 'm' when -mpcrel is in effect.
! `T' is for operands that satisfy 's' when -mpcrel is not in effect. */
#define EXTRA_CONSTRAINT(OP,CODE) \
(((CODE) == 'S') \
--- 735,742 ----
`Q' means address register indirect addressing mode.
`S' is for operands that satisfy 'm' when -mpcrel is in effect.
! `T' is for operands that satisfy 's' when -mpcrel is not in effect.
! `U' is for register offset addressing. */
#define EXTRA_CONSTRAINT(OP,CODE) \
(((CODE) == 'S') \
*************** extern enum reg_class regno_reg_class[];
*** 755,761 ****
? (GET_CODE (OP) == MEM \
&& GET_CODE (XEXP (OP, 0)) == REG) \
: \
! 0)))
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
--- 756,768 ----
? (GET_CODE (OP) == MEM \
&& GET_CODE (XEXP (OP, 0)) == REG) \
: \
! (((CODE) == 'U') \
! ? (GET_CODE (OP) == MEM \
! && GET_CODE (XEXP (OP, 0)) == PLUS \
! && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
! && GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT) \
! : \
! 0))))
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.