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[arm] Fix thumb register allocation failure
- From: Paul Brook <paul at codesourcery dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard Earnshaw <rearnsha at arm dot com>
- Date: Wed, 7 Apr 2004 21:09:17 +0100
- Subject: [arm] Fix thumb register allocation failure
- Organization: CodeSourcery
The patch below fixes a register allocation failure when compiling for thumb.
When the code below is compiled with gcc -mthumb -O2 -fno-omit-frame pointer
combine keep the argument registers (r0-r3) live up until the call to z. r7
is use for the frame pointer, which leaves only 3 register available. This is
insufficient to perform the doubleword add.
The fix is make CLASS_LIKELY_SPILLED_P return true for LO_REGS.
Tested with cross-compiler to arm-none-elf.
Ok?
Paul
void z(int, int *);
int foo(int a, int b, int c, int d, long long *q)
{
int p;
*q=*q+1;
z (a+b+c+d, &p);
}
2004-04-07 Paul Brook <paul@codesourcery.com>
* arm.h (CLASS_LIKELY_SPILLED_P): Define.
Index: config/arm/arm.h
===================================================================
RCS file: /var/cvsroot/gcc-cvs/gcc/gcc/config/arm/arm.h,v
retrieving revision 1.228
diff -u -p -r1.228 arm.h
--- a/config/arm/arm.h 24 Mar 2004 17:20:13 -0000 1.228
+++ b/config/arm/arm.h 7 Apr 2004 18:02:22 -0000
@@ -1373,6 +1373,13 @@ enum reg_class
|| reg_classes_intersect_p (VFP_REGS, (CLASS)) \
: 0)
+/* We need to define this for LO_REGS on thumb. Otherwise we can end up
+ using r0-r4 for function arguments, r7 for the stack frame and don't
+ have enough left over to do doubleword arithmetic. */
+#define CLASS_LIKELY_SPILLED_P(CLASS) \
+ ((TARGET_THUMB && (CLASS) == LO_REGS) \
+ || (CLASS) == CC_REG)
+
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
#define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)