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Re: Patch: IA64 inline integer division

> (define_insn "extendhfdf2"
>    [(set (match_operand:DF 0 "fr_register_operand" "=f")
>  	(float_extend:DF (match_operand:HF 1 "gr_register_operand" "r")))]
>    ""
>    "setf.exp %0 = %1")

After some more investigation I think we have been going about this
wrong.  While setf.exp is useful, it can only set values of 2^N.  IA64
also has setf.s and setf.d which can be used to copy any SFmode or
DFmode value from a general register to a floating point register.  The
general register just needs to contain the appropriate 32 or 64 bit
pattern for a single prec. or double prec. floating point constant.

setf.exp is used in the division code because

	mov r2 = 0xffdd
	setf.exp f11 = r2

is slightly faster than:

	movl r2 = -0x3fc0000000000000
	setf.exp f11 = r2

because the mov instruction is shorter than the movl instruction.

But both accomplish the same thing and the second form is more general
because one can use it for any DFmode value.

So I think we should forget about HFmode and create a way to for movsf &
movdf to handle arbitrary constants.  I'm not sure how to do this yet
but it seems like it should be possible.

Steve Ellcey

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