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Re: head: MIPS: A workaround for the R4000 divide/shift errata
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: "Maciej W. Rozycki" <macro at ds2 dot pg dot gda dot pl>
- Cc: Eric Christopher <echristo at redhat dot com>, gcc-patches at gcc dot gnu dot org
- Date: Mon, 01 Mar 2004 18:25:00 +0000
- Subject: Re: head: MIPS: A workaround for the R4000 divide/shift errata
- References: <Pine.LNX.4.55.0402191819520.3794@jurand.ds.pg.gda.pl><87hdxmizre.fsf@redhat.com><Pine.LNX.4.55.0402192203320.3794@jurand.ds.pg.gda.pl><87brnumzht.fsf@redhat.com> <mailpost.1077233012.25220@news-sj1-1><yov5d68aab2x.fsf@ldt-sj3-010.sj.broadcom.com><yov58yiyaay8.fsf@ldt-sj3-010.sj.broadcom.com><1077234678.4140.19.camel@dzur.sfbay.redhat.com><Pine.LNX.4.55.0402201608080.29033@jurand.ds.pg.gda.pl><87brnr8p8w.fsf@redhat.com><Pine.LNX.4.55.0402221641340.26503@jurand.ds.pg.gda.pl><yov51xomd26d.fsf@ldt-sj3-010.sj.broadcom.com><1077507519.3636.39.camel@dzur.sfbay.redhat.com><87r7wmxl71.fsf@redhat.com><Pine.LNX.4.55.0402231340020.1245@jurand.ds.pg.gda.pl><Pine.LNX.4.55.0402240820040.25829@jurand.ds.pg.gda.pl><87ishwoodv.fsf@redhat.com><Pine.LNX.4.55.0402241153320.25829@jurand.ds.pg.gda.pl><87oerj7y1r.fsf@redhat.com><Pine.LNX.4.55.0403011213590.1962@jurand.ds.pg.gda.pl>
"Maciej W. Rozycki" <macro@ds2.pg.gda.pl> writes:
>> I was going to add a comment about why the nop was needed even for
>> -mcheck-zero-division. In the end, I figured it was easier just to
>> force the division into the delay slot as previously discussed.
>> Working on that now.
>
> Please wait for a while. I have two more patches for this area to
> reflect events that happened meanwhile.
Too late. ;) I'd already tested the patch below. I thought about giving
way to your new division change, but I think doing this first will lead
to a cleaner implementation. Will reply separately saying why.
Bootstrapped & regression tested on mips-sgi-irix6.5. Also tested on
mips64vrel-elf to test the mips16 bits. Applied to trunk.
Richard
* config/mips/mips.c (mips_output_division): Use the division
instruction to fill the delay slot of a zero check.
(mips_idiv_insns): Adjust accordingly.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.388
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.388 mips.c
*** config/mips/mips.c 28 Feb 2004 20:27:42 -0000 1.388
--- config/mips/mips.c 28 Feb 2004 21:24:16 -0000
*************** mips_idiv_insns (void)
*** 1359,1370 ****
count = 1;
if (TARGET_CHECK_ZERO_DIV)
! {
! if (TARGET_MIPS16)
! count += 2;
! else
! count += 3;
! }
if (TARGET_FIX_R4000)
count++;
return count;
--- 1359,1365 ----
count = 1;
if (TARGET_CHECK_ZERO_DIV)
! count += 2;
if (TARGET_FIX_R4000)
count++;
return count;
*************** mips_output_conditional_branch (rtx insn
*** 9225,9240 ****
const char *
mips_output_division (const char *division, rtx *operands)
{
! const char *s = division;
if (TARGET_CHECK_ZERO_DIV)
{
- output_asm_insn (s, operands);
-
if (TARGET_MIPS16)
! s = "bnez\t%2,1f\n\tbreak\t7\n1:";
else
! s = "bne\t%2,%.,1f%#\n\tbreak\t7\n1:";
}
if (TARGET_FIX_R4000)
{
--- 9220,9241 ----
const char *
mips_output_division (const char *division, rtx *operands)
{
! const char *s;
+ s = division;
if (TARGET_CHECK_ZERO_DIV)
{
if (TARGET_MIPS16)
! {
! output_asm_insn (s, operands);
! s = "bnez\t%2,1f\n\tbreak\t7\n1:";
! }
else
! {
! output_asm_insn ("%(bne\t%2,%.,1f", operands);
! output_asm_insn (s, operands);
! s = "break\t7%)\n1:";
! }
}
if (TARGET_FIX_R4000)
{