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fix bootstrap failure on powerpc-darwin
- From: gkeating at geoffk5 dot apple dot com (Geoffrey Keating)
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 4 Feb 2004 15:07:56 -0800 (PST)
- Subject: fix bootstrap failure on powerpc-darwin
GCC was occasionally (depending on environment size, I think) crashing
compiling reload in stage1. This fixes it.
Bootstrap & test on powerpc-darwin running, I'll commit when it finishes.
--
- Geoffrey Keating <geoffk@apple.com>
===File ~/patches/gcc-reloadhardregnonregsoflow.patch=======
Index: ChangeLog
===================================================================
RCS file: /cvs/gcc/gcc/gcc/ChangeLog,v
retrieving revision 2.2644
diff -u -p -u -p -r2.2644 ChangeLog
--- ChangeLog 4 Feb 2004 20:00:37 -0000 2.2644
+++ ChangeLog 4 Feb 2004 23:01:19 -0000
@@ -1,3 +1,8 @@
+2004-02-04 Geoffrey Keating <geoffk@apple.com>
+
+ * reload.c (find_equiv_reg): When checking for register overlap,
+ don't index hard_regno_nregs with a pseudo-reg.
+
2004-02-04 Kazu Hirata <kazu@cs.umass.edu>
* config/darwin.c, config/darwin.h, config/freebsd-spec.h,
Index: reload.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/reload.c,v
retrieving revision 1.234
diff -u -p -u -p -r1.234 reload.c
--- reload.c 2 Feb 2004 00:17:17 -0000 1.234
+++ reload.c 4 Feb 2004 23:01:19 -0000
@@ -6587,16 +6587,15 @@ find_equiv_reg (rtx goal, rtx insn, enum
/* Reject registers that overlap GOAL. */
- if (!goal_mem && !goal_const
- && regno + (int) hard_regno_nregs[regno][mode] > valueno
- && regno < valueno + (int) hard_regno_nregs[valueno][mode])
- return 0;
-
if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER)
nregs = hard_regno_nregs[regno][mode];
else
nregs = 1;
valuenregs = hard_regno_nregs[valueno][mode];
+
+ if (!goal_mem && !goal_const
+ && regno + nregs > valueno && regno < valueno + valuenregs)
+ return 0;
/* Reject VALUE if it is one of the regs reserved for reloads.
Reload1 knows how to reuse them anyway, and it would get
============================================================