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Better use of tm/icm in the s390 backend
- From: Andreas Krebbel <krebbel1 at de dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 4 Feb 2004 13:35:21 +0100
- Subject: Better use of tm/icm in the s390 backend
- Organization: IBM Entwicklung GmbH
- Reply-to: Andreas dot Krebbel at web dot de
Hello,
the following patch fixes few issues about the usage of tm and icm in the
s390 backend.
The icm (insert under mask) instruction is expressed
through an (unspec ...) in rtl syntax. If this unspec expression is emitted
to early in the code creation process no optimization on the resulting pattern
can take place because the optimizer steps can't handle it. The new insns
"*extendsiqi2_short_displ" and "extendqidi2_short_displ" provide a rtl
pattern for the icm which later on must be replaced by an unspec through a forced
split pattern.
For comparisons like x<0 usually the tm (test under mask)
instruction is choosen. For 64 bit the pattern for a (zero_extract:DI ... was missing.
I've added the pattern which is enabled for a 64 bit target only.
Bootstrapped and regtested on s390-ibm-linux and s390x-ibm-linux.
OK?
-Andreas-
2004-02-04 Andreas Krebbel <krebbel1@de.ibm.com>
* config/s390/s390.md ("*tmqidi_ext", "*extendqidi2_short_displ",
"*extendsiqi2_short_displ"): New insn.
("*tmqisi_ext"): Renamed old "*tmqi_ext".
Index: gcc/config/s390/s390.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.md,v
retrieving revision 1.94
diff -p -c -r1.94 s390.md
*** gcc/config/s390/s390.md 1 Feb 2004 21:21:41 -0000 1.94
--- gcc/config/s390/s390.md 4 Feb 2004 12:10:31 -0000
***************
*** 433,445 ****
}
[(set_attr "op_type" "RI")])
! (define_insn "*tmqi_ext"
[(set (reg 33)
(compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S")
(match_operand:SI 1 "const_int_operand" "n,n")
(match_operand:SI 2 "const_int_operand" "n,n"))
(const_int 0)))]
! "s390_match_ccmode(insn, CCTmode)
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
{
--- 433,445 ----
}
[(set_attr "op_type" "RI")])
! (define_insn "*tmqisi_ext"
[(set (reg 33)
(compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S")
(match_operand:SI 1 "const_int_operand" "n,n")
(match_operand:SI 2 "const_int_operand" "n,n"))
(const_int 0)))]
! "!TARGET_64BIT && s390_match_ccmode(insn, CCTmode)
&& INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
{
***************
*** 451,456 ****
--- 451,475 ----
}
[(set_attr "op_type" "SI,SIY")])
+ (define_insn "*tmqidi_ext"
+ [(set (reg 33)
+ (compare (zero_extract:DI (match_operand:QI 0 "memory_operand" "Q,S")
+ (match_operand:SI 1 "const_int_operand" "n,n")
+ (match_operand:SI 2 "const_int_operand" "n,n"))
+ (const_int 0)))]
+ "TARGET_64BIT && s390_match_ccmode(insn, CCTmode)
+ && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0
+ && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8"
+ {
+ int block = (1 << INTVAL (operands[1])) - 1;
+ int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]);
+
+ operands[2] = GEN_INT (block << shift);
+ return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2";
+ }
+ [(set_attr "op_type" "SI,SIY")])
+
+
; Test-under-Mask instructions
(define_insn "*tmdi_mem"
***************
*** 2392,2401 ****
"lgb\t%0,%1"
[(set_attr "op_type" "RXY")])
! (define_split
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
! "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
(clobber (reg:CC 33))])
--- 2411,2422 ----
"lgb\t%0,%1"
[(set_attr "op_type" "RXY")])
! (define_insn_and_split "*extendqidi2_short_displ"
[(set (match_operand:DI 0 "register_operand" "")
(sign_extend:DI (match_operand:QI 1 "s_operand" "")))]
! "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
! "#"
! "&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
(clobber (reg:CC 33))])
***************
*** 2454,2463 ****
"lb\t%0,%1"
[(set_attr "op_type" "RXY")])
! (define_split
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
! "!TARGET_LONG_DISPLACEMENT && !reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
(clobber (reg:CC 33))])
--- 2475,2486 ----
"lb\t%0,%1"
[(set_attr "op_type" "RXY")])
! (define_insn_and_split "*extendsiqi2_short_displ"
[(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:QI 1 "s_operand" "")))]
! "!TARGET_LONG_DISPLACEMENT"
! "#"
! "&& reload_completed"
[(parallel
[(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
(clobber (reg:CC 33))])