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Fix PR target/11475


This is an ICE on valid code at -O.  The combiner generates an IOR pattern 
between SUBREGs in HImode, which is matched against:

(define_insn "*movhi_lo_sum"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(ior:HI (match_operand:HI 1 "arith_operand" "%r")
                (match_operand:HI 2 "arith_operand" "I")))]
  ""
  "or\t%1, %2, %0")

and accepted.  Then reload dies on the insn, because it of course can't do 
anything to turn a register into a constant described by the "I" constraint.

Fixed by fixing the pattern. Bootstrapped/regtested on sparc64-sun-solaris2.9 
and sparc-sun-solaris2.8 (3.4 branch, except Ada).


Mark, although the bug is not a regression, I'd like to put the patch on the 
3.4 branch too because it's a dumb mistake, which is explicitly mentioned in 
the manual:

     For an operand that must be a constant, you must be sure to either
     use `"immediate_operand"' for PREDICATE, or make the instruction
     pattern's extra condition require a constant, or both.  You cannot
     expect the constraints to do this work!  If the constraints allow
     only constants, but the predicate allows something else, the
     compiler will crash when that case arises.


2004-01-29  Eric Botcazou  <ebotcazou@libertysurf.fr>

	PR target/11475
	* config/sparc/sparc.md (movhi_lo_sum): Tighten predicates.


2004-01-29  Eric Botcazou  <ebotcazou@libertysurf.fr>

	* gcc.c-torture/compile/20040129-1.c: New test.


-- 
Eric Botcazou
Index: config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.md,v
retrieving revision 1.196
diff -u -p -r1.196 sparc.md
--- config/sparc/sparc.md	14 Jan 2004 09:48:30 -0000	1.196
+++ config/sparc/sparc.md	29 Jan 2004 09:22:09 -0000
@@ -1,8 +1,8 @@
 ;; Machine description for SPARC chip for GCC
 ;;  Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
-;;  1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+;;  1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
 ;;  Contributed by Michael Tiemann (tiemann@cygnus.com)
-;;  64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
+;;  64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
 ;;  at Cygnus Support.
 
 ;; This file is part of GCC.
@@ -1818,8 +1818,8 @@
 ;; We always work with constants here.
 (define_insn "*movhi_lo_sum"
   [(set (match_operand:HI 0 "register_operand" "=r")
-	(ior:HI (match_operand:HI 1 "arith_operand" "%r")
-                (match_operand:HI 2 "arith_operand" "I")))]
+	(ior:HI (match_operand:HI 1 "register_operand" "%r")
+                (match_operand:HI 2 "small_int" "I")))]
   ""
   "or\t%1, %2, %0")
 
/* PR target/11475 */
/* Origin: <heinrich.brand@fujitsu-siemens.com> */

/* This used to fail on SPARC because of a broken pattern.  */

#pragma pack(2)

struct
{
  unsigned char G936:7;
  unsigned short G937:6;
  unsigned int :4;
  unsigned short :14;
  unsigned int G938:8;
  unsigned int :30;
  unsigned short :16;
  unsigned int :18;
  unsigned short G939:9;
} G928b;

void TestG928(void)
{
  G928b.G936 |= G928b.G939;
}

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