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Disable PowerPC unaligned load/store optimizations temporarily
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 27 Jan 2004 17:05:36 -0500
- Subject: Disable PowerPC unaligned load/store optimizations temporarily
The recent patch to split unaligned doubleword loads and stores
into word loads and stores ironically fails when compiling libobjc sendmsg
for 64-bit AIX. This patch disables the code to restore bootstrap while
we debug the failure. It also tweaks the coding style.
David
* config/rs6000/rs6000.c (rs6000_emit_move): #if 0 splitting
slow, unaligned loads and stores while debugging. Fix formatting.
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.582
diff -c -p -r1.582 rs6000.c
*** rs6000.c 26 Jan 2004 17:40:06 -0000 1.582
--- rs6000.c 27 Jan 2004 21:55:29 -0000
*************** rs6000_emit_move (rtx dest, rtx source,
*** 3426,3431 ****
--- 3426,3432 ----
adjust_address (operands[1], SImode, 4));
return;
}
+ #if 0
else if (mode == DImode && TARGET_POWERPC64
&& GET_CODE (operands[0]) == REG
&& GET_CODE (operands[1]) == MEM && optimize > 0
*************** rs6000_emit_move (rtx dest, rtx source,
*** 3435,3450 ****
: MEM_ALIGN (operands[1]))
&& !no_new_pseudos)
{
- rtx mem;
rtx reg = gen_reg_rtx (SImode);
! mem = adjust_address (operands[1], SImode, 0);
! emit_insn (gen_rtx_SET (SImode, reg, mem));
! reg = simplify_gen_subreg (DImode, reg, SImode, 0);
emit_insn (gen_insvdi (operands[0], GEN_INT (32), const0_rtx, reg));
reg = gen_reg_rtx (SImode);
! mem = adjust_address (operands[1], SImode, 4);
! emit_insn (gen_rtx_SET (SImode, reg, mem));
! reg = simplify_gen_subreg (DImode, reg, SImode, 0);
emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32), reg));
return;
}
--- 3436,3450 ----
: MEM_ALIGN (operands[1]))
&& !no_new_pseudos)
{
rtx reg = gen_reg_rtx (SImode);
! emit_insn (gen_rtx_SET (SImode, reg,
! adjust_address (operands[1], SImode, 0)));
! reg = simplify_gen_subreg (DImode, reg, SImode, 0);
emit_insn (gen_insvdi (operands[0], GEN_INT (32), const0_rtx, reg));
reg = gen_reg_rtx (SImode);
! emit_insn (gen_rtx_SET (SImode, reg,
! adjust_address (operands[1], SImode, 4)));
! reg = simplify_gen_subreg (DImode, reg, SImode, 0);
emit_insn (gen_insvdi (operands[0], GEN_INT (32), GEN_INT (32), reg));
return;
}
*************** rs6000_emit_move (rtx dest, rtx source,
*** 3457,3471 ****
: MEM_ALIGN (operands[0]))
&& !no_new_pseudos)
{
- rtx mem;
rtx reg = gen_reg_rtx (DImode);
! emit_move_insn (reg, gen_rtx_LSHIFTRT (DImode, operands[1], GEN_INT (32)));
! mem = adjust_address (operands[0], SImode, 0);
! emit_move_insn (mem, simplify_gen_subreg (SImode, reg, DImode, 0));
! mem = adjust_address (operands[0], SImode, 4);
! emit_move_insn (mem, simplify_gen_subreg (SImode, operands[1], DImode, 0));
return;
}
if (!no_new_pseudos)
{
--- 3457,3472 ----
: MEM_ALIGN (operands[0]))
&& !no_new_pseudos)
{
rtx reg = gen_reg_rtx (DImode);
! emit_move_insn (reg,
! gen_rtx_LSHIFTRT (DImode, operands[1], GEN_INT (32)));
! emit_move_insn (adjust_address (operands[0], SImode, 0),
! simplify_gen_subreg (SImode, reg, DImode, 0));
! emit_move_insn (adjust_address (operands[0], SImode, 4),
! simplify_gen_subreg (SImode, operands[1], DImode, 0));
return;
}
+ #endif
if (!no_new_pseudos)
{
*************** function_arg_pass_by_reference (CUMULATI
*** 4500,4506 ****
}
static void
! rs6000_move_block_from_reg(int regno, rtx x, int nregs)
{
int i;
enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
--- 4501,4507 ----
}
static void
! rs6000_move_block_from_reg (int regno, rtx x, int nregs)
{
int i;
enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;