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Re: PATCH:[darwin] fix load of a misaligned double word
- From: "Hartmut Penner" <HPENNER at de dot ibm dot com>
- To: David Edelsohn <dje at makai dot watson dot ibm dot com>
- Cc: fjahanian at apple dot com, gcc-patches at gcc dot gnu dot org, Geoff Keating <geoffk at geoffk dot org>, lucier at math dot purdue dot edu, pinskia at physics dot uc dot edu, "Ulrich Weigand" <Ulrich dot Weigand at de dot ibm dot com>
- Date: Tue, 20 Jan 2004 16:33:31 +0100
- Subject: Re: PATCH:[darwin] fix load of a misaligned double word
Hello,
did some discussion with Ulrich about reload and problem
we have here with unsatisfied constraint. He pointed out, that this
is a secondary reload problem.
It is, that reloads generates a reload move, which itself is
invalid. For this cases, the reload_in/outM insns and the
SECONDARY_RELOAD_CLASS macro are in place. This we used
on S/390 to resolve same strange addressing problem, like there with
the movti insn.
Patch for our problem here would look like this.
Did bootstrap it on linux ppc64.
If this is in place, any ? and ! in the constraints would work out,
the only would have influence on the code quality.
OK to commit (3.4, head) ?
regards, Hartmut
2004-01-20 Hartmut Penner <hpenner@de.ibm.com>
* gcc/config/rs6000/rs6000.c (secondary_reload_class)
Allocate BASE_REG for reload_{in|out}df
* gcc/config/rs6000/rs6000.md (reload_outdf) New.
(reload_indf) New.
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.580
diff -u -p -r1.580 rs6000.c
--- rs6000.c 18 Jan 2004 15:45:51 -0000 1.580
+++ rs6000.c 20 Jan 2004 07:05:08 -0000
@@ -8375,6 +8398,16 @@ secondary_reload_class (enum reg_class c
}
else
regno = -1;
+
+ /* Invalid 'Y' addresses in movdf insn need secondary reload. */
+ if (TARGET_POWERPC64
+ && mode == DFmode
+ && reg_classes_intersect_p (GENERAL_REGS, class)
+ && GET_CODE (in) == MEM
+ && !word_offset_memref_operand (in, mode))
+ {
+ return BASE_REGS;
+ }
/* We can place anything into GENERAL_REGS and can put GENERAL_REGS
into anything. */
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.284
diff -u -p -r1.284 rs6000.md
--- rs6000.md 12 Jan 2004 18:37:40 -0000 1.284
+++ rs6000.md 20 Jan 2004 07:05:16 -0000
@@ -8163,7 +8163,7 @@
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
(define_insn "*movdf_hardfloat64"
- [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,??r,!r,f,f,m,!cl,!r,!r,!r,!r")
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!r,!r,!r")
(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,G,H,F"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
&& (gpc_reg_operand (operands[0], DFmode)
@@ -8183,6 +8183,7 @@
[(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
(set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])
+
(define_insn "*movdf_softfloat64"
[(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
(match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
@@ -8201,6 +8202,43 @@
nop"
[(set_attr "type" "load,store,*,*,*,*,*,*,*")
(set_attr "length" "4,4,4,4,4,8,12,16,4")])
+
+/* Secondary reload, for reloads of movdf insn,
+ if address does not satisfy the 'Y' constraint.
+*/
+
+(define_expand "reload_outdf"
+ [(parallel [(match_operand:DF 0 "memory_operand" "")
+ (match_operand:DF 1 "register_operand" "")
+ (match_operand:DI 2 "register_operand" "=&b")])]
+ "TARGET_POWERPC64"
+{
+ if (TARGET_64BIT)
+ emit_move_insn (operands[2], XEXP (operands[0], 0));
+ else
+ emit_move_insn (gen_lowpart_SUBREG (SImode, operands[2]),
+ XEXP (operands[0], 0));
+ operands[0] = replace_equiv_address (operands[0], operands[2]);
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
+(define_expand "reload_indf"
+ [(parallel [(match_operand:DF 0 "register_operand" "")
+ (match_operand:DF 1 "memory_operand" "")
+ (match_operand:DI 2 "register_operand" "=&b")])]
+ "TARGET_POWERPC64"
+{
+ if (TARGET_64BIT)
+ emit_move_insn (operands[2], XEXP (operands[1], 0));
+ else
+ emit_move_insn (gen_lowpart_SUBREG (SImode, operands[2]),
+ XEXP (operands[1], 0));
+ operands[1] = replace_equiv_address (operands[1], operands[2]);
+ emit_move_insn (operands[0], operands[1]);
+ DONE;
+})
+
(define_expand "movtf"
[(set (match_operand:TF 0 "general_operand" "")