Re: [PATCH] New port m32r-linux target

[Nick Clifton <nickc at redhat dot com>]

Hi Kazuhiro,

> This patch is for m32r-linux and PIC support.

I have applied all of this patch apart from one section:

> gcc/ChangeLog
> 2003-12-22 Kazuhiro Inaoka < inaoka dot kazuhiro at renesas dot com >
>
>       Support PIC. Support m32r-linux target, Support TRAMPOLINE.
>       * config.sub: Added little-endian-target.

This file is not in the gcc/ directory.  It is a top level file and it
is maintained separately from gcc.  I cannot approve changes to this
file, so you will need to submit a separate patch to:

  config-patches@gnu.org


Also, your ChangeLog entry included this line:

>         * doc/invoke.texi: Add -mflush-func, -mflush-trap options.

But there was no patch to add this documentation.  I have taken the
libiberty of generating my own patch (attached) which is my guess as
to what was intended here.  Please let me know if you have any problems
with it.


Finally, I have also generated a small gcc web page patch (attached)
to announce the available of an m32r-linux target in gcc 3.4.  I have
not mentioned the support for little-endian code generation since I
think you said that this was still unfinished ?

> gcc/ChangeLog        
> 2003-12-31  Kazuhiro Inaoka  <inaoka.kazuhiro@renesas.com>
> 
> 	* config.gcc: Added m32r-linux m32rle-elf and m32le-linux targets.
> 	* doc/invoke.texi: Document -mflush-func, -mflush-trap options.
> 	Also add documentation for -mdebug, -malign-loops, -missue-rate,
> 	and -mbranch-cost options.
> 	* config/m32r/t-linux: New file: m32r-linux support.
> 	* config/m32r/xm-linux.h: Likewise.
> 	* config/m32r/xm-m32r.h: Likewise.
> 	* config/m32r/linux.h: Likewise.
> 	* config/m32r/little.h: New file: Little endian code generation
> 	support.
> 	* config/m32r/m32r-protos.h (m32r_legitimize_pic_address,
> 	m32r_legitimate_pic_operand_p, load_pic_register): Add
> 	prototypes.
> 	* config/m32r/m32r.c (m32r_init): Add options for cache-flush.
> 	(addr24_operand): Changes for PIC code generation.
> 	* config/m32r/m32r.h (LABEL_ALIGN): Define to calculate PNOP
> 	length at labels.
> 	(ASM_SPEC): Add PIC support.
> 	(FUNCTION_PROFILER): New define.
> 	(TRAMPOLINE_SIZE, INITIALIZE_TRAMPOLINE): Changed to support
> 	trampoline.
> 	(CONDITIONAL_REGISTER_USAGE, CONSTANT_ADDRESS_P,
> 	 LEGITIMIZE_ADDRESS, JUMP_TABLES_IN_TEXT_SECTION,
> 	 PIC_OFFSET_TABLE_REGNUM, FINALIZE_PIC, LEGITIMATE_PIC_OPERAND_P,
> 	 ASM_OUTPUT_ADDR_DIFF_ELT, CASE_VECTOR_MODE): Define for PIC.
> 	(move_src_operand, m32r_compute_frame_size, m32r_expand_prologue,
> 	 m32r_finalize_pic): Changes for PIC and profile support.
> 	(global_offset_table, load_pic_register, m32r_legitimate_pic_operand_p,
> 	 m32r_legitimize_pic_address): Add for PIC support.
> 	(m32r_file_start): Changed for little-endian-target.
> 	* config/m32r/m32r.md (mvqi, movhi, movsi, movdi, movsf, movdf,
> 	tablejump, tablejump_insn, call, call_value, call_value_via_label):
> 	Changes for PIC.
> 	(pic_load_addr, get_pc, builtin_setjmp_receiver): Added for PIC.
> 	(flush_icache): Changes for cache-flush trap.

Approved and applied.

Cheers
        Nick

Index: doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.375
diff -c -3 -p -r1.375 invoke.texi
*** doc/invoke.texi	30 Dec 2003 15:00:43 -0000	1.375
--- doc/invoke.texi	31 Dec 2003 10:14:32 -0000
*************** in the following sections.
*** 400,407 ****
  -mno-crt0  -mrelax}
  
  @emph{M32R/D Options}
! @gccoptlist{-m32r2 -m32rx -m32r -mcode-model=@var{model-type} @gol
! -msdata=@var{sdata-type}  -G @var{num}}
  
  @emph{M88K Options}
  @gccoptlist{-m88000  -m88100  -m88110  -mbig-pic @gol
--- 400,415 ----
  -mno-crt0  -mrelax}
  
  @emph{M32R/D Options}
! @gccoptlist{-m32r2 -m32rx -m32r @gol
! -mdebug @gol
! -malign-loops -mno-align-loops @gol
! -missue-rate=@var{number} @gol
! -mbranch-cost=@var{number} @gol
! -mmodel=@var{code-size-model-type} @gol
! -msdata=@var{sdata-type} @gol
! -mno-flush-func -mflush-func=@var{name} @gol
! -mno-flush-trap -mflush-trap=@var{number} @gol
! -G @var{num}}
  
  @emph{M88K Options}
  @gccoptlist{-m88000  -m88100  -m88110  -mbig-pic @gol
*************** Generate code for the M32R/X@.
*** 6834,6841 ****
  @opindex m32r
  Generate code for the M32R@.  This is the default.
  
! @item -mcode-model=small
! @opindex mcode-model=small
  Assume all objects live in the lower 16MB of memory (so that their addresses
  can be loaded with the @code{ld24} instruction), and assume all subroutines
  are reachable with the @code{bl} instruction.
--- 6842,6849 ----
  @opindex m32r
  Generate code for the M32R@.  This is the default.
  
! @item -mmodel=small
! @opindex mmodel=small
  Assume all objects live in the lower 16MB of memory (so that their addresses
  can be loaded with the @code{ld24} instruction), and assume all subroutines
  are reachable with the @code{bl} instruction.
*************** This is the default.
*** 6844,6857 ****
  The addressability of a particular object can be set with the
  @code{model} attribute.
  
! @item -mcode-model=medium
! @opindex mcode-model=medium
  Assume objects may be anywhere in the 32-bit address space (the compiler
  will generate @code{seth/add3} instructions to load their addresses), and
  assume all subroutines are reachable with the @code{bl} instruction.
  
! @item -mcode-model=large
! @opindex mcode-model=large
  Assume objects may be anywhere in the 32-bit address space (the compiler
  will generate @code{seth/add3} instructions to load their addresses), and
  assume subroutines may not be reachable with the @code{bl} instruction
--- 6852,6865 ----
  The addressability of a particular object can be set with the
  @code{model} attribute.
  
! @item -mmodel=medium
! @opindex mmodel=medium
  Assume objects may be anywhere in the 32-bit address space (the compiler
  will generate @code{seth/add3} instructions to load their addresses), and
  assume all subroutines are reachable with the @code{bl} instruction.
  
! @item -mmodel=large
! @opindex mmodel=large
  Assume objects may be anywhere in the 32-bit address space (the compiler
  will generate @code{seth/add3} instructions to load their addresses), and
  assume subroutines may not be reachable with the @code{bl} instruction
*************** All modules should be compiled with the 
*** 6892,6897 ****
--- 6900,6948 ----
  Compiling with different values of @var{num} may or may not work; if it
  doesn't the linker will give an error message---incorrect code will not be
  generated.
+ 
+ @item -mdebug
+ @opindex -mdebug
+ Makes the M32R specific code in the compiler display some statistics
+ that might help in debugging programs.
+ 
+ @item -malign-loops
+ @opindex
+ Align all loops to a 32-byte boundary.
+ 
+ @item -mno-align-loops
+ @opindex
+ Do not enforce a 32-byte alignment for loops.  This is the default.
+ 
+ @item -missue-rate=@var{number}
+ @opindex
+ Issue @var{number} instructions per cycle.  @var{number} can only be 1
+ or 2.
+ 
+ @item -mbranch-cost=@var{number}
+ @opindex
+ @var{number} can only be 1 or 2.  If it is 1 then branches will be
+ prefered over conditional code, if it is 2, then the opposite will
+ apply.
+ 
+ @item -mflush-trap=@var{number}
+ @opindex
+ Specifies the trap number to use to flush the cache.  The default is
+ 12.  Valid numbers are between 0 and 15 inclusive.
+ 
+ @item -mno-flush-trap
+ @opindex
+ Specifies that the cache cannot be flushed by using a trap.
+ 
+ @item -mflush-func=@var{name}
+ @opindex
+ Specifies the name of the operating system function to call to flush
+ the cache.  The default is @emph{_flush_cache}, but a function call
+ will only be used if a trap is not available.
+ 
+ @item -mno-flush-func
+ @opindex
+ Indicates that there is no OS function for flushing the cache.
  
  @end table
  

Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-3.4/changes.html,v
retrieving revision 1.78
diff -c -3 -p -r1.78 changes.html
*** changes.html	23 Dec 2003 19:47:33 -0000	1.78
--- changes.html	31 Dec 2003 10:15:27 -0000
***************
*** 421,429 ****
      <li>Further small performance improvements.</li>
    </ul>
  
! <h4>M32</h4>
    <ul>
      <li>Support for the M32R/2 processor has been added by Renesas.</li>
    </ul>
  
  <h4>M68000</h4>
--- 421,431 ----
      <li>Further small performance improvements.</li>
    </ul>
  
! <h4>M32R</h4>
    <ul>
      <li>Support for the M32R/2 processor has been added by Renesas.</li>
+     <li>Support for an M32R Linux target and PIC code generation has
+         been added by Renesas.</li>
    </ul>
  
  <h4>M68000</h4>