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Fix ICE in compiling glibc
- From: Jan Hubicka <jh at suse dot cz>
- To: gcc-patches at gcc dot gnu dot org, rth at redhat dot com, aj at suse dot de
- Date: Mon, 29 Dec 2003 01:01:18 +0100
- Subject: Fix ICE in compiling glibc
Hi,
the following testcases cause reload failure because combine propagate st(0)
into asm input operand of statement and reload is not able to use the same
register for output operand. For 3.3 it works because we don't combine hard reg
loads, for mainline we need hard reg to be CLASS_LIKELY_SPILLED_P, that looks
like sane to set it for FP top and FP second registers.
Bootstrapped/regtested i386, OK?
Honza
extern long double acosl (long double __x);
extern long double atan2l (long double __y, long double __x) ;
extern __inline long double __atan2l (long double __y, long double __x)
{
register long double __value;
__asm __volatile__ ("fpatan" : "=t" (__value) : "0" (__x), "u" (__y) : "st(1)");
return __value;
}
extern __inline long double acosl (long double __x)
{
return __atan2l (__builtin_sqrtl (1.0 - __x * __x), __x);
}
extern void
check_float (long double computed);
static void
acos_test (void)
{
check_float (acosl (-1.125L));
}
static void
atan2_test (void)
{
check_float (atan2l (-0.00756827042671106339L, -.001792735857538728036L));
}
int
main (int argc, char **argv)
{
acos_test ();
atan2_test ();
return 0;
}
2003-12-29 Jan Hubicka <jh@suse.cz>
* i386.h (CLASS_LIKELY_SPILLED_P): Return true for FP_TOP_REG/FP_SECOND_REG
*** /aux/hubicka/egcs2/gcc/gcc/config/i386/i386.h Sat Aug 23 23:18:57 2003
--- i386.h Mon Dec 29 00:51:37 2003
*************** enum reg_class
*** 1601,1607 ****
|| ((CLASS) == BREG) \
|| ((CLASS) == AD_REGS) \
|| ((CLASS) == SIREG) \
! || ((CLASS) == DIREG))
/* Return a class of registers that cannot change FROM mode to TO mode.
--- 1581,1589 ----
|| ((CLASS) == BREG) \
|| ((CLASS) == AD_REGS) \
|| ((CLASS) == SIREG) \
! || ((CLASS) == DIREG) \
! || ((CLASS) == FP_TOP_REG) \
! || ((CLASS) == FP_SECOND_REG))
/* Return a class of registers that cannot change FROM mode to TO mode.