This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH] - Use of powerpc 64bit instructions in 32bit ABI
>>>>> Eric Botcazou writes:
Eric> It cures the pessimization for my original testcase. However, I think this
Eric> is not enough for the following slightly tweaked case:
Eric> We start with:
Eric> (parallel:QI [
Eric> (expr_list (reg:DI %i0)
Eric> (const_int 0 [0x0]))
Eric> ])
Eric> and the new transformation generates
Eric> (reg:QI 107)
Eric> so emit_group_store emits a move between the two locations, which requires 9
Eric> more insns in the 01.rtl file than the original code, because this time no
Eric> reg is spilled so a combination of ASHIFT, SUBREG, AND and OR is used. This
Eric> is fully recovered at -O2, but not at -O1.
In some sense, this is what the change is trying to produce. Yes,
it's more instructions, but it generally is much faster for any modern
processor to perform these computations in registers instead of accessing
(cache) memory. If you only are focussing on instruction counts, you are
overlooking the actual performance. Nine instructions is a lot, but that
is in the 01.rtl final, not the final output (even at -O1).
It is expensive for a processor to write out one or more values to
memory and then read back a value with a different width -- often the
processor cannot short-circuit that type of operation.
David