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Re: [PATCH] - Use of powerpc 64bit instructions in 32bit ABI


> *** function.c	1 Nov 2003 02:23:44 -0000	1.465
> --- function.c	3 Nov 2003 20:45:50 -0000
> *************** assign_parms (tree fndecl)
> *** 4703,4708 ****
> --- 4703,4717 ----
>
>   	 Set DECL_RTL to that place.  */
>
> +       if (GET_CODE (entry_parm) == PARALLEL && nominal_mode != BLKmode)
> + 	{
> + 	  /* Objects the size of a register can be combined in registers */
> + 	  rtx parmreg = gen_reg_rtx (nominal_mode);
> + 	  emit_group_store (parmreg, entry_parm, TREE_TYPE (parm),
> + 			    int_size_in_bytes (TREE_TYPE (parm)));
> + 	  SET_DECL_RTL (parm, parmreg);
> + 	}
> +
>         if (nominal_mode == BLKmode
>   #ifdef BLOCK_REG_PADDING
>
>   	  || (locate.where_pad == (BYTES_BIG_ENDIAN ? upward : downward)
>

This hunk introduced a pessimization on SPARC64 (verified at -O2) and 
probably on SPARC too.  Here is an example (extracted from a dg-compat 
testcase which segfaults after the patch, maybe a latent bug elsewhere):

typedef struct { _Complex char a; } Scc1;

void checkScc1 (Scc1 x, _Complex char y)
{
  if (x.a != y)
    abort ();
}


'x' is passed in a register and a stack slot is reserved (64-bit ABI). This 
is specified by the back-end with 'entry_parm' set to

(parallel:CQI [
        (expr_list (reg:DI %i0 [ x ])
            (const_int 0 [0x0]))
    ])

Now the new code generates:

(concat:CQI (reg:QI 107)
    (reg:QI 108))

for 'parmreg' so emit_group_store needs to spill %i0, which generates more 
instructions, and it spills it to the frame instead of spilling it to the 
reserved stack slot, which takes more space in the frame.


I think the code should be guarded by severe sanity checks.

-- 
Eric Botcazou


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