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[committed] Patch to fix PR target/12727
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 30 Nov 2003 19:33:24 +0000
- Subject: [committed] Patch to fix PR target/12727
This patch fixes g++.dg/eh/registers1.C for big-endian mips2 targets
(aka PR 12727).
If we're generating 32-bit MIPS code, and the target supports sdc1,
the prologue will use it to save a pair of floating-point registers.
At the moment, the frame information for this store will just be a
single DFmode set. But that isn't right for big-endian targets
since paired FP registers are always ordered little-endian.
Patch tested on mipsisa64-elf, mips64-elf, mips-elf, mips64vrel-elf,
mips-sgi-irix6.5, etc. Installed as obvious enough.
Richard
PR target/12727
* config/mips/mips.c (mips_save_reg): Fix frame information for sdc1
on 32-bit big-endian targets.
Common subdirectories: config/mips.sibcall/CVS and config/mips/CVS
diff -upd config/mips.sibcall/mips.c config/mips/mips.c
--- config/mips.sibcall/mips.c Sat Nov 29 16:01:35 2003
+++ config/mips/mips.c Sat Nov 29 16:52:01 2003
@@ -6554,11 +6554,15 @@ mips_frame_set (rtx mem, rtx reg)
static void
mips_save_reg (rtx reg, rtx mem)
{
- if (GET_MODE (reg) == DFmode && mips_split_64bit_move_p (mem, reg))
+ if (GET_MODE (reg) == DFmode && !TARGET_FLOAT64)
{
rtx x1, x2;
- mips_split_64bit_move (mem, reg);
+ if (mips_split_64bit_move_p (mem, reg))
+ mips_split_64bit_move (mem, reg);
+ else
+ emit_move_insn (mem, reg);
+
x1 = mips_frame_set (mips_subword (mem, 0), mips_subword (reg, 0));
x2 = mips_frame_set (mips_subword (mem, 1), mips_subword (reg, 1));
mips_set_frame_expr (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x1, x2)));