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PowerPC mfcrf fix


	Generation of MFCRF was testing rs6000_cpu, which is set based on
the tuning value, not the architecture.  This would cause problems if one
is trying to generate code for G4 architecture but tune for G5.  The
appended patch converts MFCRF to a target flag, after discussions with
Geoff and Zack.

	This patch also changes "Don't" to "Do not" in a number of places.

Bootstrapped with no new regressions.

David


	* config/rs6000/rs6000.h (MASK_MFCRF): New.
	(TARGET_MFCRF): Test target_flags, not processor type.
	(TARGET_SWITCHES): Add mfcrf and no-mfcrf.
	Change Don't to Do not.
	* config/rs6000/rs6000.c (processors_target_table): Add MASK_MFCRF
	to power4, 970, G5.

Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.550
diff -c -p -r1.550 rs6000.c
*** rs6000.c	14 Nov 2003 20:05:34 -0000	1.550
--- rs6000.c	28 Nov 2003 04:44:06 -0000
*************** rs6000_override_options (const char *def
*** 645,651 ****
  	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
  	    POWER_MASKS},
  	 {"power4", PROCESSOR_POWER4,
!             MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
              POWER_MASKS},
  	 {"powerpc", PROCESSOR_POWERPC,
  	    MASK_POWERPC | MASK_NEW_MNEMONICS,
--- 645,651 ----
  	    MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS,
  	    POWER_MASKS},
  	 {"power4", PROCESSOR_POWER4,
!             MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS | MASK_MFCRF,
              POWER_MASKS},
  	 {"powerpc", PROCESSOR_POWERPC,
  	    MASK_POWERPC | MASK_NEW_MNEMONICS,
*************** rs6000_override_options (const char *def
*** 753,762 ****
  	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
  	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
  	 {"970", PROCESSOR_POWER4,
! 	    MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS,
  	    POWER_MASKS},
  	 {"G5", PROCESSOR_POWER4,
! 	    MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS,
  	    POWER_MASKS}};
  
    const size_t ptt_size = ARRAY_SIZE (processor_target_table);
--- 753,762 ----
  	    MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS,
  	    POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64},
  	 {"970", PROCESSOR_POWER4,
! 	    MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
  	    POWER_MASKS},
  	 {"G5", PROCESSOR_POWER4,
! 	    MASK_POWERPC | POWERPC_OPT_MASKS | MASK_NEW_MNEMONICS | MASK_MFCRF,
  	    POWER_MASKS}};
  
    const size_t ptt_size = ARRAY_SIZE (processor_target_table);
Index: rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.300
diff -c -p -r1.300 rs6000.h
*** rs6000.h	12 Nov 2003 22:52:09 -0000	1.300
--- rs6000.h	28 Nov 2003 04:44:06 -0000
*************** extern int target_flags;
*** 187,193 ****
  /* Return small structures in memory (as the AIX ABI requires).  */
  #define MASK_AIX_STRUCT_RET	0x00040000
  
! /* The only remaining free bits are 0x00780000. sysv4.h uses
     0x00800000 -> 0x40000000, and 0x80000000 is not available
     because target_flags is signed.  */
  
--- 187,196 ----
  /* Return small structures in memory (as the AIX ABI requires).  */
  #define MASK_AIX_STRUCT_RET	0x00040000
  
! /* Use single field mfcr instruction.  */
! #define MASK_MFCRF		0x00080000
! 
! /* The only remaining free bits are 0x00700000. sysv4.h uses
     0x00800000 -> 0x40000000, and 0x80000000 is not available
     because target_flags is signed.  */
  
*************** extern int target_flags;
*** 210,215 ****
--- 213,229 ----
  #define TARGET_ALTIVEC		(target_flags & MASK_ALTIVEC)
  #define TARGET_AIX_STRUCT_RET	(target_flags & MASK_AIX_STRUCT_RET)
  
+ /* Define TARGET_MFCRF if the target assembler supports the optional
+    field operand for mfcr and the target processor supports the
+    instruction.  */
+ 
+ #ifdef HAVE_AS_MFCRF
+ #define TARGET_MFCRF		(target_flags & MASK_MFCRF)
+ #else
+ #define TARGET_MFCRF 0
+ #endif
+ 
+ 
  #define TARGET_32BIT		(! TARGET_64BIT)
  #define TARGET_HARD_FLOAT	(! TARGET_SOFT_FLOAT)
  #define TARGET_UPDATE		(! TARGET_NO_UPDATE)
*************** extern int target_flags;
*** 259,277 ****
    {"powerpc-gpopt",	MASK_POWERPC | MASK_PPC_GPOPT,			\
  			N_("Use PowerPC General Purpose group optional instructions")},\
    {"no-powerpc-gpopt",	- MASK_PPC_GPOPT,				\
! 			N_("Don't use PowerPC General Purpose group optional instructions")},\
    {"powerpc-gfxopt",	MASK_POWERPC | MASK_PPC_GFXOPT,			\
  			N_("Use PowerPC Graphics group optional instructions")},\
    {"no-powerpc-gfxopt",	- MASK_PPC_GFXOPT,				\
! 			N_("Don't use PowerPC Graphics group optional instructions")},\
    {"powerpc64",		MASK_POWERPC64,					\
  			N_("Use PowerPC-64 instruction set")},		\
    {"no-powerpc64",	- MASK_POWERPC64,				\
! 			N_("Don't use PowerPC-64 instruction set")},	\
    {"altivec",		MASK_ALTIVEC ,					\
  			N_("Use AltiVec instructions")},		\
    {"no-altivec",	- MASK_ALTIVEC ,					\
! 			N_("Don't use AltiVec instructions")},	\
    {"new-mnemonics",	MASK_NEW_MNEMONICS,				\
  			N_("Use new mnemonics for PowerPC architecture")},\
    {"old-mnemonics",	-MASK_NEW_MNEMONICS,				\
--- 273,291 ----
    {"powerpc-gpopt",	MASK_POWERPC | MASK_PPC_GPOPT,			\
  			N_("Use PowerPC General Purpose group optional instructions")},\
    {"no-powerpc-gpopt",	- MASK_PPC_GPOPT,				\
! 			N_("Do not use PowerPC General Purpose group optional instructions")},\
    {"powerpc-gfxopt",	MASK_POWERPC | MASK_PPC_GFXOPT,			\
  			N_("Use PowerPC Graphics group optional instructions")},\
    {"no-powerpc-gfxopt",	- MASK_PPC_GFXOPT,				\
! 			N_("Do not use PowerPC Graphics group optional instructions")},\
    {"powerpc64",		MASK_POWERPC64,					\
  			N_("Use PowerPC-64 instruction set")},		\
    {"no-powerpc64",	- MASK_POWERPC64,				\
! 			N_("Do not use PowerPC-64 instruction set")},	\
    {"altivec",		MASK_ALTIVEC ,					\
  			N_("Use AltiVec instructions")},		\
    {"no-altivec",	- MASK_ALTIVEC ,					\
! 			N_("Do not use AltiVec instructions")},	\
    {"new-mnemonics",	MASK_NEW_MNEMONICS,				\
  			N_("Use new mnemonics for PowerPC architecture")},\
    {"old-mnemonics",	-MASK_NEW_MNEMONICS,				\
*************** extern int target_flags;
*** 282,292 ****
    {"fp-in-toc",		- MASK_NO_FP_IN_TOC,				\
  			N_("Place floating point constants in TOC")},	\
    {"no-fp-in-toc",	MASK_NO_FP_IN_TOC,				\
! 			N_("Don't place floating point constants in TOC")},\
    {"sum-in-toc",	- MASK_NO_SUM_IN_TOC,				\
  			N_("Place symbol+offset constants in TOC")},	\
    {"no-sum-in-toc",	MASK_NO_SUM_IN_TOC,				\
! 			N_("Don't place symbol+offset constants in TOC")},\
    {"minimal-toc",	MASK_MINIMAL_TOC,				\
  			"Use only one TOC entry per procedure"},	\
    {"minimal-toc",	- (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC),	\
--- 296,306 ----
    {"fp-in-toc",		- MASK_NO_FP_IN_TOC,				\
  			N_("Place floating point constants in TOC")},	\
    {"no-fp-in-toc",	MASK_NO_FP_IN_TOC,				\
! 			N_("Do not place floating point constants in TOC")},\
    {"sum-in-toc",	- MASK_NO_SUM_IN_TOC,				\
  			N_("Place symbol+offset constants in TOC")},	\
    {"no-sum-in-toc",	MASK_NO_SUM_IN_TOC,				\
! 			N_("Do not place symbol+offset constants in TOC")},\
    {"minimal-toc",	MASK_MINIMAL_TOC,				\
  			"Use only one TOC entry per procedure"},	\
    {"minimal-toc",	- (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC),	\
*************** extern int target_flags;
*** 294,302 ****
    {"no-minimal-toc",	- MASK_MINIMAL_TOC,				\
  			N_("Place variable addresses in the regular TOC")},\
    {"hard-float",	- MASK_SOFT_FLOAT,				\
! 			N_("Use hardware fp")},				\
    {"soft-float",	MASK_SOFT_FLOAT,				\
! 			N_("Do not use hardware fp")},			\
    {"multiple",		MASK_MULTIPLE,					\
  			N_("Generate load/store multiple instructions")},	\
    {"no-multiple",	- MASK_MULTIPLE,				\
--- 308,316 ----
    {"no-minimal-toc",	- MASK_MINIMAL_TOC,				\
  			N_("Place variable addresses in the regular TOC")},\
    {"hard-float",	- MASK_SOFT_FLOAT,				\
! 			N_("Use hardware floating point")},		\
    {"soft-float",	MASK_SOFT_FLOAT,				\
! 			N_("Do not use hardware floating point")},	\
    {"multiple",		MASK_MULTIPLE,					\
  			N_("Generate load/store multiple instructions")},	\
    {"no-multiple",	- MASK_MULTIPLE,				\
*************** extern int target_flags;
*** 312,322 ****
    {"fused-madd",	- MASK_NO_FUSED_MADD,				\
  			N_("Generate fused multiply/add instructions")},\
    {"no-fused-madd",	MASK_NO_FUSED_MADD,				\
! 			N_("Don't generate fused multiply/add instructions")},\
    {"sched-prolog",      MASK_SCHED_PROLOG,                              \
  			""},						\
    {"no-sched-prolog",   -MASK_SCHED_PROLOG,                             \
! 			N_("Don't schedule the start and end of the procedure")},\
    {"sched-epilog",      MASK_SCHED_PROLOG,                              \
  			""},						\
    {"no-sched-epilog",   -MASK_SCHED_PROLOG,                             \
--- 326,336 ----
    {"fused-madd",	- MASK_NO_FUSED_MADD,				\
  			N_("Generate fused multiply/add instructions")},\
    {"no-fused-madd",	MASK_NO_FUSED_MADD,				\
! 			N_("Do not generate fused multiply/add instructions")},\
    {"sched-prolog",      MASK_SCHED_PROLOG,                              \
  			""},						\
    {"no-sched-prolog",   -MASK_SCHED_PROLOG,                             \
! 			N_("Do not schedule the start and end of the procedure")},\
    {"sched-epilog",      MASK_SCHED_PROLOG,                              \
  			""},						\
    {"no-sched-epilog",   -MASK_SCHED_PROLOG,                             \
*************** extern int target_flags;
*** 326,334 ****
    {"svr4-struct-return", - MASK_AIX_STRUCT_RET,				\
  			N_("Return small structures in registers (SVR4 default)")},\
    {"no-aix-struct-return", - MASK_AIX_STRUCT_RET,			\
! 			""},\
    {"no-svr4-struct-return", MASK_AIX_STRUCT_RET,			\
! 			""},\
    SUBTARGET_SWITCHES							\
    {"",			TARGET_DEFAULT | MASK_SCHED_PROLOG,		\
  			""}}
--- 340,352 ----
    {"svr4-struct-return", - MASK_AIX_STRUCT_RET,				\
  			N_("Return small structures in registers (SVR4 default)")},\
    {"no-aix-struct-return", - MASK_AIX_STRUCT_RET,			\
! 			""},						\
    {"no-svr4-struct-return", MASK_AIX_STRUCT_RET,			\
! 			""},						\
!   {"mfcrf",		MASK_MFCRF,					\
! 			N_("Generate single field mfcr instruction")},	\
!   {"no-mfcrf",		- MASK_MFCRF,					\
! 			N_("Do not generate single field mfcr instruction")},\
    SUBTARGET_SWITCHES							\
    {"",			TARGET_DEFAULT | MASK_SCHED_PROLOG,		\
  			""}}
*************** extern enum rs6000_nop_insertion rs6000_
*** 529,544 ****
  #define DEFAULT_SCHED_FINISH_NOP_INSERTION_SCHEME          \
    (rs6000_cpu == PROCESSOR_POWER4 ? sched_finish_regroup_exact : sched_finish_none)
  
- /* Define TARGET_MFCRF if the target assembler supports the optional
-    field operand for mfcr and the target processor supports the
-    instruction.  */
- 
- #ifdef HAVE_AS_MFCRF
- #define TARGET_MFCRF (rs6000_cpu == PROCESSOR_POWER4)
- #else
- #define TARGET_MFCRF 0
- #endif
- 
  #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128)
  #define TARGET_ALTIVEC_ABI rs6000_altivec_abi
  #define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave
--- 547,552 ----
*************** extern enum rs6000_nop_insertion rs6000_
*** 555,561 ****
     defined, is executed once just after all the command options have
     been parsed.
  
!    Don't use this macro to turn on various extra optimizations for
     `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.
  
     On the RS/6000 this is used to define the target cpu type.  */
--- 563,569 ----
     defined, is executed once just after all the command options have
     been parsed.
  
!    Do not use this macro to turn on various extra optimizations for
     `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.
  
     On the RS/6000 this is used to define the target cpu type.  */


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