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[patch] gcc-3.4/changes.html: Make target-specific improvementsmore readable.


Hi,

Attached is a patch to make target-specific improvements more readable
by putting items together for each target just like
gcc-3.2/changes.html.  (I personally think gcc-3.2/changes.html looks
better than gcc-3.3/changes.html as far as target-specific
improvements section is concerned.)

The patch removes certain redundancy like

  The x86 back end has had some noticeable work done to it.

Also,

  Support for <code>long long</code> has been added to the H8/300 port.

becomes

  Support for <code>long long</code> has been added.

as the applicable target can be determined by looking at the heading.

OK to apply?

Kazu Hirata

Index: changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-3.4/changes.html,v
retrieving revision 1.64
diff -c -1 -2 -r1.64 changes.html
*** changes.html	14 Nov 2003 16:19:56 -0000	1.64
--- changes.html	15 Nov 2003 19:15:00 -0000
***************
*** 326,435 ****
    </ul>
  
  <h3>Fortran</h3>
  
    <ul>
      <li>Fortran improvements are listed in              
      <a href="http://gcc.gnu.org/onlinedocs/g77/News.html";>
      the Fortran documentation</a>.</li>
    </ul>
  
  <h2>New Targets and Target Specific Improvements</h2>
  
    <ul>
-     <li>Bernardo Innocenti (Develer&nbsp;S.r.l.) has contributed
-     the <code>m68k-uclinux</code> target, based on former work done
-     by Paul Dale (SnapGear&nbsp;Inc.).  Code generation for the
-     <code>ColdFire</code> processors family has been enhanced and extended
-     to support the MCF&nbsp;53xx and MCF&nbsp;54xx cores, integrating
-     former work done by Peter Barada (Motorola).</li>
- 
-     <li>Support for the Mitsubishi V850E1 processor has been added.
-     This is a variant of the V850E processor with some additional
-     debugging instructions.</li>
-     
      <li>Nicolas Pitre has contributed his hand-coded floating-point support
      code for ARM.  It is both significantly smaller and faster than the 
      existing C-based implementation, even when building applications for 
      Thumb.  The <code>arm-elf</code> configuration has been converted to use
      the new code.</li>
  
      <li>Support for the Intel's iWMMXt architecture, a second
      generation XScale processor, has been addded to the ARM port.
      Enabled at run time with the <code>-mcpu=iwmmxt</code> command
      line switch.</li>
      
      <li>A new ARM target has been added: <code>arm-wince-pe</code>.  This is
      similar to the <code>arm-pe</code> target, but it defaults to using the
      APCS32 ABI.</li>
  
      <li>The existing ARM pipeline description has been converted to
      the use the <a
      href="http://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.html";>DFA
      processor pipeline model</a>. There is not much change in code
      performance, but the description is now <a
      href="http://gcc.gnu.org/onlinedocs/gccint/Comparison-of-the-two-descriptions.html";>easier
      to understand</a>.</li>
      
-     <li>The x86 back end has had some noticeable work done to it.
-     <ul>
-       <li>Tuning for K8 core is available via <code>-march=k8</code> and <code>-mcpu=k8</code></li>
-       <li>Scalar SSE code generation carefully avoids reformatting penalties,
-           hidden dependencies and minimizes the number of uops generated on
-           both Intel and AMD CPUs.</li>
-       <li>Conditional jump elimination is now more aggressive on modern CPUs.</li>
-       <li>The Athlon and K8 ports have been converted to use the DFA
-           processor pipeline description.</li>
-       <li>Optimization of indirect tail calls is now possible in a similar
-         fashion as direct sibcall optimization.</li>
-       <li>Further small performance improvements.</li>
-     </ul></li>
-     <li>Support for the SH2E processor has been added to the SH port.
-     Enabled at run time with the <code>-m2e</code> command line
-     switch, or at configure time by specifying sh2e as the machine
-     part of the target triple.</li>
-     
      <li>Support for the Cirrus EP9312 Maverick floating point
      co-processor added to the ARM port.  Enabled at run time with the
      <code>-mcpu=ep9312</code> command line switch.  Note however that
      the multilibs to support this chip are currently disabled in
      <code>gcc/config/arm/t-arm-elf</code>, so if you want to enable their
      production you will have to uncomment the entries in that
      file.</li>
!     
!     <li>Support for <code>long long</code> has been added to the
!     H8/300 port.</li>
  
!     <li>Support for <code>saveall</code> attribute has been added to
!     the H8/300 port.</li>
  
      <li>Support for the RM7000 and RM9000 processors has been added to the
      MIPS port.  It is activated by the <code>-march</code> compiler option
      and should work with any MIPS I (<code>mips-*</code>) or MIPS III
      (<code>mips64-*</code>) configuration.</li>
  
      <li><a name="mips_abi">n32 and n64 MIPS targets now pass all
      structures by value.</a>  While this change brings GCC closer
      to ABI compliance, it will unfortunately break binary compatibility
      with earlier releases.  A structure used to be passed by reference if:
      <ul>
        <li>the target was big-endian;</li>
        <li>the structure was bigger than 8 bytes;</li>
        <li>the structure's size was not a multiple of 8 bytes; and</li>
        <li>the first word of the structure would have been passed in
  	  a register.</li>
      </ul>
      Note that only big-endian n32 &amp; n64 targets (such as IRIX 6) are
      affected.</li>
  
      <li>More processor configuration options for Xtensa processors are
      supported:
      <ul>
        <li>the <code>ABS</code> instruction is now optional;</li>
        <li>the <code>ADDX*</code> and <code>SUBX*</code> instructions are
        now optional;</li>
        <li>an experimental <code>CONST16</code> instruction can be used to
        synthesize constants instead of loading them from constant pools.</li>
      </ul>
      These and other Xtensa processor configuration options can no longer
      be enabled or disabled by command-line options; the processor
      configuration must be specified by the <code>xtensa-config.h</code>
--- 326,453 ----
    </ul>
  
  <h3>Fortran</h3>
  
    <ul>
      <li>Fortran improvements are listed in              
      <a href="http://gcc.gnu.org/onlinedocs/g77/News.html";>
      the Fortran documentation</a>.</li>
    </ul>
  
  <h2>New Targets and Target Specific Improvements</h2>
  
+ <h4>ARM</h4>
    <ul>
      <li>Nicolas Pitre has contributed his hand-coded floating-point support
      code for ARM.  It is both significantly smaller and faster than the 
      existing C-based implementation, even when building applications for 
      Thumb.  The <code>arm-elf</code> configuration has been converted to use
      the new code.</li>
  
      <li>Support for the Intel's iWMMXt architecture, a second
      generation XScale processor, has been addded to the ARM port.
      Enabled at run time with the <code>-mcpu=iwmmxt</code> command
      line switch.</li>
      
      <li>A new ARM target has been added: <code>arm-wince-pe</code>.  This is
      similar to the <code>arm-pe</code> target, but it defaults to using the
      APCS32 ABI.</li>
  
      <li>The existing ARM pipeline description has been converted to
      the use the <a
      href="http://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.html";>DFA
      processor pipeline model</a>. There is not much change in code
      performance, but the description is now <a
      href="http://gcc.gnu.org/onlinedocs/gccint/Comparison-of-the-two-descriptions.html";>easier
      to understand</a>.</li>
      
      <li>Support for the Cirrus EP9312 Maverick floating point
      co-processor added to the ARM port.  Enabled at run time with the
      <code>-mcpu=ep9312</code> command line switch.  Note however that
      the multilibs to support this chip are currently disabled in
      <code>gcc/config/arm/t-arm-elf</code>, so if you want to enable their
      production you will have to uncomment the entries in that
      file.</li>
!   </ul>
! 
! <h4>H8/300</h4>
!   <ul>
!     <li>Support for <code>long long</code> has been added.</li>
  
!     <li>Support for <code>saveall</code> attribute has been added.</li>
!   </ul>
! 
! <h4>IA-32</h4>
!   <ul>
!     <li>Tuning for K8 core is available via <code>-march=k8</code> and <code>-mcpu=k8</code></li>
!     <li>Scalar SSE code generation carefully avoids reformatting penalties,
!         hidden dependencies and minimizes the number of uops generated on
!         both Intel and AMD CPUs.</li>
!     <li>Conditional jump elimination is now more aggressive on modern CPUs.</li>
!     <li>The Athlon and K8 ports have been converted to use the DFA
!         processor pipeline description.</li>
!     <li>Optimization of indirect tail calls is now possible in a similar
!       fashion as direct sibcall optimization.</li>
!     <li>Further small performance improvements.</li>
!   </ul>
  
+ <h4>M68000</h4>
+   <ul>
+     <li>Bernardo Innocenti (Develer&nbsp;S.r.l.) has contributed
+     the <code>m68k-uclinux</code> target, based on former work done
+     by Paul Dale (SnapGear&nbsp;Inc.).  Code generation for the
+     <code>ColdFire</code> processors family has been enhanced and extended
+     to support the MCF&nbsp;53xx and MCF&nbsp;54xx cores, integrating
+     former work done by Peter Barada (Motorola).</li>
+   </ul>
+ 
+ <h4>MIPS</h4>
+   <ul>
      <li>Support for the RM7000 and RM9000 processors has been added to the
      MIPS port.  It is activated by the <code>-march</code> compiler option
      and should work with any MIPS I (<code>mips-*</code>) or MIPS III
      (<code>mips64-*</code>) configuration.</li>
  
      <li><a name="mips_abi">n32 and n64 MIPS targets now pass all
      structures by value.</a>  While this change brings GCC closer
      to ABI compliance, it will unfortunately break binary compatibility
      with earlier releases.  A structure used to be passed by reference if:
      <ul>
        <li>the target was big-endian;</li>
        <li>the structure was bigger than 8 bytes;</li>
        <li>the structure's size was not a multiple of 8 bytes; and</li>
        <li>the first word of the structure would have been passed in
  	  a register.</li>
      </ul>
      Note that only big-endian n32 &amp; n64 targets (such as IRIX 6) are
      affected.</li>
+   </ul>
  
+ <h4>SuperH</h4>
+   <ul>
+     <li>Support for the SH2E processor has been added to the SH port.
+     Enabled at run time with the <code>-m2e</code> command line
+     switch, or at configure time by specifying sh2e as the machine
+     part of the target triple.</li>
+   </ul>
+ 
+ <h4>V850</h4>
+   <ul>
+     <li>Support for the Mitsubishi V850E1 processor has been added.
+     This is a variant of the V850E processor with some additional
+     debugging instructions.</li>
+   </ul>
+ 
+ <h4>Xtensa</h4>
+   <ul>
      <li>More processor configuration options for Xtensa processors are
      supported:
      <ul>
        <li>the <code>ABS</code> instruction is now optional;</li>
        <li>the <code>ADDX*</code> and <code>SUBX*</code> instructions are
        now optional;</li>
        <li>an experimental <code>CONST16</code> instruction can be used to
        synthesize constants instead of loading them from constant pools.</li>
      </ul>
      These and other Xtensa processor configuration options can no longer
      be enabled or disabled by command-line options; the processor
      configuration must be specified by the <code>xtensa-config.h</code>


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