This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: Another look at the ARM division routine


On 12 Nov 2003, Ian Lance Taylor wrote:

> FYI, Steve's original code looks like this:
> 
> #ifndef	__OPTIMIZE_SIZE__
> 	rsbs	r3, r3, #31
> 	addne	r3, r3, r3, lsl #1
> 	mov	r0, #0
> 	addne	pc, pc, r3, lsl #2
> 	nop
> 	.set	shift, 32
> 	.rept	32
> 	.set	shift, shift - 1
> 	cmp	r2, divisor, lsl #shift
> 	adc	r0, r0, r0
> 	subcs	r2, r2, divisor, lsl #shift
> 	.endr
> #else
> 	mov	r0, #0
> Loop:
> 	cmp	r2, divisor, lsl r3
> 	adc	r0, r0, r0
> 	subcs	r2, r2, divisor, lsl r3
> 	subs	r3, r3, #1
> 	bpl	Loop
> #endif
> 
> I dropped this, because there is no reason to ever expect
> __OPTIMIZE_SIZE__ to be defined when lib1funcs.asm is assembled.  But
> I can easily add it back if you think it would be appropriate.

If you're to discriminate based on __OPTIMIZE_SIZE__ I'd suggest keeping the 
original code which is likely to be a little faster than the dumb 1 bit 
loop.


Nicolas


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]