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[committed] Trampoline fix for hppa64


This problem was detected by the failure of the new trampoline-1.c
testcase on hppa64-hp-hpux11.11.

Cache lines on PA 2.0 machines 64 bytes.  The old code did two cache line
flushes.  The lines were identified by a pair of addresses differing by
32 bytes (a carry over from the PA 1.x code).  The code in the trampoline
was 24 bytes long, offset 32 bytes from the start of the trampoline.  As
a result, the trampoline code didn't bounce when the trampoline started
16 or 24 bytes into a cache line.

Corrected by using a 64 byte offset for the pair of line flushes.

Tested on hppa64-hp-hpux11.11 with no regressions.  Installed to the trunk.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)

2003-11-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* pa.h (TRAMPOLINE_TEMPLATE): Fix flushing of cache lines when
	generating 64-bit code.

Index: config/pa/pa.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.h,v
retrieving revision 1.205
diff -u -3 -p -r1.205 pa.h
--- config/pa/pa.h	29 Oct 2003 21:44:16 -0000	1.205
+++ config/pa/pa.h	11 Nov 2003 15:48:04 -0000
@@ -993,7 +993,7 @@ extern int may_call_alloca;
 
 #define TRAMPOLINE_TEMPLATE(FILE) 					\
   {									\
-    if (! TARGET_64BIT)							\
+    if (!TARGET_64BIT)							\
       {									\
 	fputs ("\tldw	36(%r22),%r21\n", FILE);			\
 	fputs ("\tbb,>=,n	%r21,30,.+16\n", FILE);			\
@@ -1052,7 +1052,7 @@ extern int may_call_alloca;
 
 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) 			\
 {									\
-  if (! TARGET_64BIT)							\
+  if (!TARGET_64BIT)							\
     {									\
       rtx start_addr, end_addr;						\
 									\
@@ -1070,9 +1070,9 @@ extern int may_call_alloca;
       start_addr = force_reg (Pmode, (TRAMP));				\
       end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32));	\
       emit_insn (gen_dcacheflush (start_addr, end_addr));		\
-      end_addr = force_reg (Pmode, plus_constant (start_addr, 32));	\
       emit_insn (gen_icacheflush (start_addr, end_addr, start_addr,	\
-				  gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\
+				  gen_reg_rtx (Pmode),			\
+				  gen_reg_rtx (Pmode)));		\
     }									\
   else									\
     {									\
@@ -1090,13 +1090,14 @@ extern int may_call_alloca;
       start_addr = memory_address (Pmode, plus_constant ((TRAMP), 24));	\
       emit_move_insn (gen_rtx_MEM (Pmode, start_addr), end_addr);	\
       /* fdc and fic only use registers for the address to flush,	\
-	 they do not accept integer displacements.  */ 			\
+	 they do not accept integer displacements.   PA 2.0 cache	\
+	 lines are 64 bytes.  */		 			\
       start_addr = force_reg (Pmode, (TRAMP));				\
-      end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32));	\
+      end_addr = force_reg (Pmode, plus_constant ((TRAMP), 64));	\
       emit_insn (gen_dcacheflush (start_addr, end_addr));		\
-      end_addr = force_reg (Pmode, plus_constant (start_addr, 32));	\
       emit_insn (gen_icacheflush (start_addr, end_addr, start_addr,	\
-				  gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\
+				  gen_reg_rtx (Pmode),			\
+				  gen_reg_rtx (Pmode)));		\
     }									\
 }
 


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