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[patch] m68k/*: Follow spelling conventions.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sat, 11 Oct 2003 10:23:08 -0400 (EDT)
- Subject: [patch] m68k/*: Follow spelling conventions.
Hi,
Attached is a patch to follow spelling conventions. Committed as
obvious.
Kazu Hirata
2003-10-11 Kazu Hirata <kazu@cs.umass.edu>
* config/m68k/lb1sf68.asm: Follow spelling conventions.
* config/m68k/m68k.c: Likewise.
* config/m68k/m68k.h: Likewise.
* config/m68k/m68k.md: Likewise.
Index: lb1sf68.asm
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68k/lb1sf68.asm,v
retrieving revision 1.9
diff -u -r1.9 lb1sf68.asm
--- lb1sf68.asm 11 Oct 2003 03:06:45 -0000 1.9
+++ lb1sf68.asm 11 Oct 2003 14:19:13 -0000
@@ -416,11 +416,11 @@
lsrl IMM (1), d0 /* shift dividend */
cmpl IMM (0x10000), d1 /* still divisor >= 2 ^ 16 ? */
jcc L4
- divu d1, d0 /* now we have 16 bit divisor */
+ divu d1, d0 /* now we have 16-bit divisor */
andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */
-/* Multiply the 16 bit tentative quotient with the 32 bit divisor. Because of
- the operand ranges, this might give a 33 bit product. If this product is
+/* Multiply the 16-bit tentative quotient with the 32-bit divisor. Because of
+ the operand ranges, this might give a 33-bit product. If this product is
greater than the dividend, the tentative quotient was too large. */
movel d2, d1
mulu d0, d1 /* low part, 32 bits */
@@ -440,7 +440,7 @@
#else /* __mcoldfire__ */
-/* Coldfire implementation of non-restoring division algorithm from
+/* ColdFire implementation of non-restoring division algorithm from
Hennessy & Patterson, Appendix A. */
link a6,IMM (-12)
moveml d2-d4,sp@
Index: m68k.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68k/m68k.c,v
retrieving revision 1.109
diff -u -r1.109 m68k.c
--- m68k.c 11 Oct 2003 06:27:35 -0000 1.109
+++ m68k.c 11 Oct 2003 14:19:15 -0000
@@ -478,7 +478,7 @@
#endif
}
- /* on Coldfire add register save into initial stack frame setup, if possible */
+ /* on ColdFire add register save into initial stack frame setup, if possible */
num_saved_regs = 0;
if (TARGET_COLDFIRE && current_frame.reg_no > 2)
num_saved_regs = current_frame.reg_no;
@@ -1667,7 +1667,7 @@
if (USE_MOVQ (i))
return MOVQ;
- /* The Coldfire doesn't have byte or word operations. */
+ /* The ColdFire doesn't have byte or word operations. */
/* FIXME: This may not be useful for the m68060 either */
if (!TARGET_COLDFIRE)
{
@@ -1982,7 +1982,7 @@
/* This is probably useless, since it loses for pushing a struct
of several bytes a byte at a time. */
/* 68k family always modifies the stack pointer by at least 2, even for
- byte pushes. The 5200 (coldfire) does not do this. */
+ byte pushes. The 5200 (ColdFire) does not do this. */
if (GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
@@ -2032,7 +2032,7 @@
return "sub%.l %0,%0";
if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
return "move%.l %1,%0";
- /* 68k family (including the 5200 coldfire) does not support byte moves to
+ /* 68k family (including the 5200 ColdFire) does not support byte moves to
from address registers. */
if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
return "move%.w %1,%0";
@@ -2452,7 +2452,7 @@
abort ();
}
-/* Output assembler code to perform a 32 bit 3 operand add. */
+/* Output assembler code to perform a 32-bit 3-operand add. */
const char *
output_addsi3 (rtx *operands)
Index: m68k.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68k/m68k.h,v
retrieving revision 1.99
diff -u -r1.99 m68k.h
--- m68k.h 11 Oct 2003 03:06:45 -0000 1.99
+++ m68k.h 11 Oct 2003 14:19:16 -0000
@@ -194,8 +194,8 @@
/* Align ints to a word boundary. This breaks compatibility with the
published ABI's for structures containing ints, but produces faster
- code on cpus with 32 bit busses (020, 030, 040, 060, CPU32+, coldfire).
- It's required for coldfire cpus without a misalignment module. */
+ code on cpus with 32-bit busses (020, 030, 040, 060, CPU32+, ColdFire).
+ It's required for ColdFire cpus without a misalignment module. */
#define MASK_ALIGN_INT (1<<13)
#define TARGET_ALIGN_INT (target_flags & MASK_ALIGN_INT)
@@ -229,7 +229,7 @@
#define MASK_COLDFIRE (MASK_5200|MASK_528x|MASK_CFV3|MASK_CFV4)
#define TARGET_COLDFIRE (target_flags & MASK_COLDFIRE)
-/* Which bits can be set by specifying a coldfire */
+/* Which bits can be set by specifying a ColdFire */
#define MASK_ALL_CF_BITS (MASK_COLDFIRE|MASK_CF_HWDIV)
/* Macro to define tables used to set the flags.
@@ -423,9 +423,9 @@
/* No data type wants to be aligned rounder than this.
Most published ABIs say that ints should be aligned on 16 bit
- boundaries, but cpus with 32 bit busses get better performance
- aligned on 32 bit boundaries. Coldfires without a misalignment
- module require 32 bit alignment. */
+ boundaries, but cpus with 32-bit busses get better performance
+ aligned on 32-bit boundaries. ColdFires without a misalignment
+ module require 32-bit alignment. */
#define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16)
/* Set this nonzero if move instructions will actually fail to work
@@ -808,7 +808,7 @@
/* If we generate an insn to push BYTES bytes,
this says how many the stack pointer really advances by.
On the 68000, sp@- in a byte insn really pushes a word.
- On the 5200 (coldfire), sp@- in a byte insn pushes just a byte. */
+ On the 5200 (ColdFire), sp@- in a byte insn pushes just a byte. */
#define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1)
/* We want to avoid trying to push bytes. */
@@ -1237,7 +1237,7 @@
&& (TARGET_68020 || (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100)) \
{ rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
-/* coldfire/5200 does not allow HImode index registers. */
+/* ColdFire/5200 does not allow HImode index registers. */
#define LEGITIMATE_INDEX_REG_P(X) \
((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
|| (! TARGET_COLDFIRE \
Index: m68k.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68k/m68k.md,v
retrieving revision 1.68
diff -u -r1.68 m68k.md
--- m68k.md 11 Oct 2003 03:06:45 -0000 1.68
+++ m68k.md 11 Oct 2003 14:19:18 -0000
@@ -548,7 +548,7 @@
;; Recognizers for btst instructions.
-;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
+;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is
;; specified as a constant, so we must disable all patterns that may extract
;; from a MEM at a constant bit position if we can't use this as a constraint.
@@ -4841,7 +4841,7 @@
; alignment of structure members is specified.
;
; The move is allowed to be odd byte aligned, because that's still faster
-; than an odd byte aligned bit field instruction.
+; than an odd byte aligned bit-field instruction.
;
(define_insn ""
[(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
@@ -4897,7 +4897,7 @@
; alignment of structure members is specified.
;
; The move is allowed to be odd byte aligned, because that's still faster
-; than an odd byte aligned bit field instruction.
+; than an odd byte aligned bit-field instruction.
;
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
@@ -4953,7 +4953,7 @@
; alignment of structure members is specified.
;
; The move is allowed to be odd byte aligned, because that's still faster
-; than an odd byte aligned bit field instruction.
+; than an odd byte aligned bit-field instruction.
;
(define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
@@ -4999,7 +4999,7 @@
return \"move%.w %1,%0\;ext%.l %0\";
}")
-;; Bit field instructions, general cases.
+;; Bit-field instructions, general cases.
;; "o,d" constraint causes a nonoffsettable memref to match the "o"
;; so that its address is reloaded.
@@ -5103,7 +5103,7 @@
"TARGET_68020 && TARGET_BITFIELD"
"bfins %3,%0{%b2:%b1}")
-;; Now recognize bit field insns that operate on registers
+;; Now recognize bit-field insns that operate on registers
;; (or at least were intended to do so).
(define_insn ""