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Simplify handling of TARGET_4300_MUL_FIX
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: echristo at redhat dot com
- Date: 16 Aug 2003 18:17:20 +0100
- Subject: Simplify handling of TARGET_4300_MUL_FIX
This patch simplifies the handling of TARGET_4300_MUL_FIX. First, the
multiplication expanders were calling gen_* functions even though the
expander's own pattern was correct. Second, we had different patterns
for TARGET_MIPS4300, but these patterns behaved just like the normal
ones unless TARGET_4300_MUL_FIX.
Tested on the same targets as before. OK to install?
Richard
* config/mips/mips.md (muldf3, mulsf3): Don't call a gen_* function.
(muldf3_internal, muldf3_r4300): Select based on TARGET_4300_MUL_FIX
rather than TARGET_MIPS4300.
(mulsf3_internal, mulsf3_r4300): Likewise.
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.187
diff -u -d -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.187 mips.md
--- config/mips/mips.md 11 Aug 2003 15:28:20 -0000 1.187
+++ config/mips/mips.md 14 Aug 2003 12:14:35 -0000
@@ -1380,87 +1359,63 @@ (define_insn "subsi3_internal_2"
;; ....................
;;
-;; Early Vr4300 silicon has a CPU bug where multiplies with certain
-;; operands may corrupt immediately following multiplies. This is a
-;; simple fix to insert NOPs.
-
(define_expand "muldf3"
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
- "
-{
- if (!TARGET_MIPS4300)
- emit_insn (gen_muldf3_internal (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_muldf3_r4300 (operands[0], operands[1], operands[2]));
- DONE;
-}")
+ "")
(define_insn "muldf3_internal"
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_MIPS4300"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_4300_MUL_FIX"
"mul.d\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "DF")])
+;; Early VR4300 silicon has a CPU bug where multiplies with certain
+;; operands may corrupt immediately following multiplies. This is a
+;; simple fix to insert NOPs.
+
(define_insn "muldf3_r4300"
[(set (match_operand:DF 0 "register_operand" "=f")
(mult:DF (match_operand:DF 1 "register_operand" "f")
(match_operand:DF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_MIPS4300"
- "*
-{
- output_asm_insn (\"mul.d\\t%0,%1,%2\", operands);
- if (TARGET_4300_MUL_FIX)
- output_asm_insn (\"nop\", operands);
- return \"\";
-}"
+ "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_4300_MUL_FIX"
+ "mul.d\\t%0,%1,%2\;nop"
[(set_attr "type" "fmul")
(set_attr "mode" "DF")
- (set_attr "length" "8")]) ;; mul.d + nop
+ (set_attr "length" "8")])
(define_expand "mulsf3"
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
"TARGET_HARD_FLOAT"
- "
-{
- if (!TARGET_MIPS4300)
- emit_insn( gen_mulsf3_internal (operands[0], operands[1], operands[2]));
- else
- emit_insn( gen_mulsf3_r4300 (operands[0], operands[1], operands[2]));
- DONE;
-}")
+ "")
(define_insn "mulsf3_internal"
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && !TARGET_MIPS4300"
+ "TARGET_HARD_FLOAT && !TARGET_4300_MUL_FIX"
"mul.s\\t%0,%1,%2"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")])
+;; See muldf3_r4300.
+
(define_insn "mulsf3_r4300"
[(set (match_operand:SF 0 "register_operand" "=f")
(mult:SF (match_operand:SF 1 "register_operand" "f")
(match_operand:SF 2 "register_operand" "f")))]
- "TARGET_HARD_FLOAT && TARGET_MIPS4300"
- "*
-{
- output_asm_insn (\"mul.s\\t%0,%1,%2\", operands);
- if (TARGET_4300_MUL_FIX)
- output_asm_insn (\"nop\", operands);
- return \"\";
-}"
+ "TARGET_HARD_FLOAT && TARGET_4300_MUL_FIX"
+ "mul.s\\t%0,%1,%2\;nop"
[(set_attr "type" "fmul")
(set_attr "mode" "SF")
- (set_attr "length" "8")]) ;; mul.s + nop
+ (set_attr "length" "8")])
;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while