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Various trivial changes to the mips port
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: 11 Aug 2003 16:27:57 +0100
- Subject: Various trivial changes to the mips port
- Fix formatting (or at least make it match surrounding code).
- Resync arg-handling code with gas.
- Declare mips_abi with the other externs.
- Add mode to the rhs of the exception_receiver pattern.
Tested on mips-sgi-irix6.5o32 & mipsisa64-elf. Installed as obvious.
Richard
* config/mips/mips.c: Various formatting fixes.
(override_options): Resync -mtune handling with gas.
(mips_issue_rate): Rearrange like mips_use_dfa_pipeline_interface.
* config/mips/mips.h: More formatting fixes.
(mips_abi): Move declaration.
* config/mips/mips.md (exception_receiver): Add mode to
unspec_volatile.
diff -cpd config/mips.3/mips.c config/mips/mips.c
*** config/mips.3/mips.c Sun Aug 10 09:55:48 2003
--- config/mips/mips.c Sun Aug 10 11:29:07 2003
*************** Boston, MA 02111-1307, USA. */
*** 57,74 ****
of EQ, NE, etc. */
enum internal_test {
! ITEST_EQ,
! ITEST_NE,
! ITEST_GT,
! ITEST_GE,
! ITEST_LT,
! ITEST_LE,
! ITEST_GTU,
! ITEST_GEU,
! ITEST_LTU,
! ITEST_LEU,
! ITEST_MAX
! };
/* Return true if it is likely that the given mode will be accessed
using only a single instruction. */
--- 57,74 ----
of EQ, NE, etc. */
enum internal_test {
! ITEST_EQ,
! ITEST_NE,
! ITEST_GT,
! ITEST_GE,
! ITEST_LT,
! ITEST_LE,
! ITEST_GTU,
! ITEST_GEU,
! ITEST_LTU,
! ITEST_LEU,
! ITEST_MAX
! };
/* Return true if it is likely that the given mode will be accessed
using only a single instruction. */
*************** override_options ()
*** 4686,4694 ****
if (mips_arch_string != 0)
mips_set_architecture (mips_parse_cpu ("-march", mips_arch_string));
- if (mips_tune_string != 0)
- mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
-
if (mips_isa_string != 0)
{
/* Handle -mipsN. */
--- 4686,4691 ----
*************** override_options ()
*** 4725,4730 ****
--- 4722,4730 ----
mips_arch_info->name);
/* Optimize for mips_arch, unless -mtune selects a different processor. */
+ if (mips_tune_string != 0)
+ mips_set_tune (mips_parse_cpu ("-mtune", mips_tune_string));
+
if (mips_tune_info == 0)
mips_set_tune (mips_arch_info);
*************** mips_issue_rate ()
*** 9909,9919 ****
{
switch (mips_tune)
{
! case PROCESSOR_R3000: return 1;
! case PROCESSOR_R5400: return 2;
! case PROCESSOR_R5500: return 2;
! case PROCESSOR_R7000: return 2;
! case PROCESSOR_R9000: return 2;
default:
return 1;
--- 9909,9919 ----
{
switch (mips_tune)
{
! case PROCESSOR_R5400:
! case PROCESSOR_R5500:
! case PROCESSOR_R7000:
! case PROCESSOR_R9000:
! return 2;
default:
return 1;
*************** const char *
*** 9948,9977 ****
mips_emit_prefetch (operands)
rtx operands[];
{
! /* For the mips32/64 architectures the hint fields are arranged
! by operation (load/store) and locality (normal/streamed/retained).
! Irritatingly, numbers 2 and 3 are reserved leaving no simple
! algorithm for figuring the hint. */
! int write = INTVAL (operands[1]);
! int locality = INTVAL (operands[2]);
! static const char * const alt[2][4] = {
! {
! "pref\t4,%a0",
! "pref\t0,%a0",
! "pref\t0,%a0",
! "pref\t6,%a0"
! },
! {
! "pref\t5,%a0",
! "pref\t1,%a0",
! "pref\t1,%a0",
! "pref\t7,%a0"
! }
! };
! return alt[write][locality];
}
--- 9948,9977 ----
mips_emit_prefetch (operands)
rtx operands[];
{
! /* For the mips32/64 architectures the hint fields are arranged
! by operation (load/store) and locality (normal/streamed/retained).
! Irritatingly, numbers 2 and 3 are reserved leaving no simple
! algorithm for figuring the hint. */
! int write = INTVAL (operands[1]);
! int locality = INTVAL (operands[2]);
! static const char * const alt[2][4] = {
! {
! "pref\t4,%a0",
! "pref\t0,%a0",
! "pref\t0,%a0",
! "pref\t6,%a0"
! },
! {
! "pref\t5,%a0",
! "pref\t1,%a0",
! "pref\t1,%a0",
! "pref\t7,%a0"
! }
! };
! return alt[write][locality];
}
diff -cpd config/mips.3/mips.h config/mips/mips.h
*** config/mips.3/mips.h Sun Aug 10 11:19:32 2003
--- config/mips/mips.h Sun Aug 10 11:29:07 2003
*************** extern enum cmp_type branch_type; /* wha
*** 114,119 ****
--- 114,120 ----
extern enum processor_type mips_arch; /* which cpu to codegen for */
extern enum processor_type mips_tune; /* which cpu to schedule for */
extern int mips_isa; /* architectural level */
+ extern int mips_abi; /* which ABI to use */
extern int mips16_hard_float; /* mips16 without -msoft-float */
extern int mips_entry; /* generate entry/exit for mips16 */
extern const char *mips_arch_string; /* for -march=<xxx> */
*************** extern const struct mips_cpu_info *mips_
*** 363,369 ****
/* We do this here because __mips is defined below \
and so we can't use builtin_define_std. */ \
if (!flag_iso) \
! builtin_define ("mips"); \
\
/* Treat _R3000 and _R4000 like register-size defines, \
which is how they've historically been used. */ \
--- 364,370 ----
/* We do this here because __mips is defined below \
and so we can't use builtin_define_std. */ \
if (!flag_iso) \
! builtin_define ("mips"); \
\
/* Treat _R3000 and _R4000 like register-size defines, \
which is how they've historically been used. */ \
*************** extern const struct mips_cpu_info *mips_
*** 379,390 ****
builtin_define ("_R3000"); \
} \
if (TARGET_FLOAT64) \
! builtin_define ("__mips_fpr=64"); \
else \
! builtin_define ("__mips_fpr=32"); \
\
if (TARGET_MIPS16) \
! builtin_define ("__mips16"); \
\
MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
--- 380,391 ----
builtin_define ("_R3000"); \
} \
if (TARGET_FLOAT64) \
! builtin_define ("__mips_fpr=64"); \
else \
! builtin_define ("__mips_fpr=32"); \
\
if (TARGET_MIPS16) \
! builtin_define ("__mips16"); \
\
MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
*************** extern const struct mips_cpu_info *mips_
*** 429,440 ****
} \
\
if (TARGET_HARD_FLOAT) \
! builtin_define ("__mips_hard_float"); \
else if (TARGET_SOFT_FLOAT) \
! builtin_define ("__mips_soft_float"); \
\
if (TARGET_SINGLE_FLOAT) \
! builtin_define ("__mips_single_float"); \
\
if (TARGET_BIG_ENDIAN) \
{ \
--- 430,441 ----
} \
\
if (TARGET_HARD_FLOAT) \
! builtin_define ("__mips_hard_float"); \
else if (TARGET_SOFT_FLOAT) \
! builtin_define ("__mips_soft_float"); \
\
if (TARGET_SINGLE_FLOAT) \
! builtin_define ("__mips_single_float"); \
\
if (TARGET_BIG_ENDIAN) \
{ \
*************** extern const struct mips_cpu_info *mips_
*** 967,974 ****
#define SUBTARGET_TARGET_SWITCHES
- extern int mips_abi;
-
#ifndef MIPS_ABI_DEFAULT
#define MIPS_ABI_DEFAULT ABI_32
#endif
--- 968,973 ----
*************** extern int mips_abi;
*** 1211,1217 ****
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
/* Describe how we implement __builtin_eh_return. */
! #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
/* Offsets recorded in opcodes are a multiple of this alignment factor.
--- 1210,1218 ----
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
/* Describe how we implement __builtin_eh_return. */
! #define EH_RETURN_DATA_REGNO(N) \
! ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
!
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
/* Offsets recorded in opcodes are a multiple of this alignment factor.
diff -cpd config/mips.3/mips.md config/mips/mips.md
*** config/mips.3/mips.md Sun Aug 10 07:44:27 2003
--- config/mips/mips.md Sun Aug 10 11:29:07 2003
*************** ld\\t%2,%1-%S1(%2)\;daddu\\t%2,%2,$31\\n
*** 8453,8459 ****
(define_insn "exception_receiver"
[(set (reg:SI 28)
! (unspec_volatile [(const_int 0)] UNSPEC_EH_RECEIVER))]
"TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)"
{ return mips_restore_gp (operands); }
[(set_attr "type" "load")
--- 8453,8459 ----
(define_insn "exception_receiver"
[(set (reg:SI 28)
! (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
"TARGET_ABICALLS && (mips_abi == ABI_32 || mips_abi == ABI_O64)"
{ return mips_restore_gp (operands); }
[(set_attr "type" "load")