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[PATCH] Fix PA PR's target/11607 and PR target/11516
- From: "John David Anglin" <dave at hiauly1 dot hia dot nrc dot ca>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 23 Jul 2003 12:08:30 -0400 (EDT)
- Subject: [PATCH] Fix PA PR's target/11607 and PR target/11516
This patch reverts the latter half of the last patch to pa.md. It contained
an error affecting the 64-bit port. My attempts at fixing this in order
to avoid potentially emitting instructions with undefined behavior hasn't
been completely successful on the 3.3 branch. I haven't had time to determine
why, so I am just reverting the problematic code.
Tested on hppa-unknown-linux-gnu and hppa64-hp-hpux11.11.
Committed to 3.3 branch and trunk.
Dave
--
J. David Anglin dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada (613) 990-0752 (FAX: 952-6602)
2003-07-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR target/11607 and PR target/11516
* pa.md (extzv, extv, insv): Revert latter half of last patch.
Index: config/pa/pa.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.md,v
retrieving revision 1.116.2.10
diff -u -3 -p -r1.116.2.10 pa.md
--- config/pa/pa.md 9 Jul 2003 05:48:17 -0000 1.116.2.10
+++ config/pa/pa.md 23 Jul 2003 05:22:12 -0000
@@ -7156,17 +7156,12 @@
FAIL;
if (TARGET_64BIT)
- {
- if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
- || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
- FAIL;
- emit_insn (gen_extzv_64 (operands[0], operands[1],
- operands[2], operands[3]));
- }
+ emit_insn (gen_extzv_64 (operands[0], operands[1],
+ operands[2], operands[3]));
else
{
- if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
- || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
+ if (! uint5_operand (operands[2], SImode)
+ || ! uint5_operand (operands[3], SImode))
FAIL;
emit_insn (gen_extzv_32 (operands[0], operands[1],
operands[2], operands[3]));
@@ -7177,8 +7172,8 @@
(define_insn "extzv_32"
[(set (match_operand:SI 0 "register_operand" "=r")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "uint32_operand" "")
- (match_operand:SI 3 "uint32_operand" "")))]
+ (match_operand:SI 2 "uint5_operand" "")
+ (match_operand:SI 3 "uint5_operand" "")))]
""
"{extru|extrw,u} %1,%3+%2-1,%2,%0"
[(set_attr "type" "shift")
@@ -7227,17 +7222,12 @@
FAIL;
if (TARGET_64BIT)
- {
- if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
- || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
- FAIL;
- emit_insn (gen_extv_64 (operands[0], operands[1],
- operands[2], operands[3]));
- }
+ emit_insn (gen_extv_64 (operands[0], operands[1],
+ operands[2], operands[3]));
else
{
- if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
- || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
+ if (! uint5_operand (operands[2], SImode)
+ || ! uint5_operand (operands[3], SImode))
FAIL;
emit_insn (gen_extv_32 (operands[0], operands[1],
operands[2], operands[3]));
@@ -7248,8 +7238,8 @@
(define_insn "extv_32"
[(set (match_operand:SI 0 "register_operand" "=r")
(sign_extract:SI (match_operand:SI 1 "register_operand" "r")
- (match_operand:SI 2 "uint32_operand" "")
- (match_operand:SI 3 "uint32_operand" "")))]
+ (match_operand:SI 2 "uint5_operand" "")
+ (match_operand:SI 3 "uint5_operand" "")))]
""
"{extrs|extrw,s} %1,%3+%2-1,%2,%0"
[(set_attr "type" "shift")
@@ -7294,22 +7284,13 @@
""
"
{
- /* PA insertion insns don't support zero length bitfields. */
- if (INTVAL (operands[2]) == 0)
- FAIL;
-
if (TARGET_64BIT)
- {
- if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 64
- || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 63)
- FAIL;
- emit_insn (gen_insv_64 (operands[0], operands[1],
- operands[2], operands[3]));
- }
+ emit_insn (gen_insv_64 (operands[0], operands[1],
+ operands[2], operands[3]));
else
{
- if ((unsigned HOST_WIDE_INT) INTVAL (operands[2]) > 32
- || (unsigned HOST_WIDE_INT) INTVAL (operands[3]) > 31)
+ if (! uint5_operand (operands[2], SImode)
+ || ! uint5_operand (operands[3], SImode))
FAIL;
emit_insn (gen_insv_32 (operands[0], operands[1],
operands[2], operands[3]));
@@ -7319,8 +7300,8 @@
(define_insn "insv_32"
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
- (match_operand:SI 1 "uint32_operand" "")
- (match_operand:SI 2 "uint32_operand" ""))
+ (match_operand:SI 1 "uint5_operand" "")
+ (match_operand:SI 2 "uint5_operand" ""))
(match_operand:SI 3 "arith5_operand" "r,L"))]
""
"@