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[patch] config/[himn]*: Fix comment typos.
- From: Kazu Hirata <kazu at cs dot umass dot edu>
- To: gcc-patches at gcc dot gnu dot org
- Date: Sun, 06 Jul 2003 19:05:30 -0400 (EDT)
- Subject: [patch] config/[himn]*: Fix comment typos.
Hi,
Attached is a patch to fix comment typos. Committed as obvious.
Kazu Hirata
2003-07-06 Kazu Hirata <kazu@cs.umass.edu>
* config/h8300/h8300.c: Fix comment typos.
* config/h8300/h8300.md: Likewise.
* config/i386/athlon.md: Likewise.
* config/i386/i386.c: Likewise.
* config/i386/pentium.md: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/itanium1.md: Likewise.
* config/ia64/itanium2.md: Likewise.
* config/m32r/m32r.md: Likewise.
* config/m68hc11/m68hc11.c: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mips/sr71k.md: Likewise.
* config/mips/t-iris5-as: Likewise.
* config/mmix/mmix.h: Likewise.
* config/ns32k/ns32k.h: Likewise.
* config/ns32k/NOTES: Fix a typo.
Index: config/h8300/h8300.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.c,v
retrieving revision 1.248
diff -u -r1.248 h8300.c
--- config/h8300/h8300.c 5 Jul 2003 18:58:40 -0000 1.248
+++ config/h8300/h8300.c 6 Jul 2003 22:59:33 -0000
@@ -1920,7 +1920,7 @@
return base_length - 2;
else
/* In SImode and SFmode, we use two mov.w instructions, so
- double the adustment. */
+ double the adjustment. */
return base_length - 4;
}
Index: config/h8300/h8300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/h8300/h8300.md,v
retrieving revision 1.228
diff -u -r1.228 h8300.md
--- config/h8300/h8300.md 2 Jul 2003 20:48:04 -0000 1.228
+++ config/h8300/h8300.md 6 Jul 2003 22:59:35 -0000
@@ -4189,7 +4189,7 @@
(pc)))]
"operands[4] = GEN_INT (- INTVAL (operands[1]));")
-;; For certain (in)equaltity comparisons against a constant, we can
+;; For certain (in)equality comparisons against a constant, we can
;; XOR the register with the constant, and test the register against
;; 0.
Index: config/i386/athlon.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/athlon.md,v
retrieving revision 1.6
diff -u -r1.6 athlon.md
--- config/i386/athlon.md 24 Apr 2003 15:53:19 -0000 1.6
+++ config/i386/athlon.md 6 Jul 2003 22:59:35 -0000
@@ -667,7 +667,7 @@
(eq_attr "type" "sseadd"))
"athlon-double,athlon-fpsched,(athlon-fadd*2)")
-;; Conversions behaves very irregulary and the scheduling is critical here.
+;; Conversions behaves very irregularly and the scheduling is critical here.
;; Take each instruction separately. Assume that the mode is always set to the
;; destination one and athlon_decode is set to the K8 versions.
Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.584
diff -u -r1.584 i386.c
--- config/i386/i386.c 5 Jul 2003 15:39:58 -0000 1.584
+++ config/i386/i386.c 6 Jul 2003 22:59:41 -0000
@@ -2608,7 +2608,7 @@
if (AGGREGATE_TYPE_P (type))
{
- /* Walk the agregates recursively. */
+ /* Walk the aggregates recursively. */
if (TREE_CODE (type) == RECORD_TYPE
|| TREE_CODE (type) == UNION_TYPE
|| TREE_CODE (type) == QUAL_UNION_TYPE)
Index: config/i386/pentium.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/pentium.md,v
retrieving revision 1.6
diff -u -r1.6 pentium.md
--- config/i386/pentium.md 26 Dec 2002 18:45:04 -0000 1.6
+++ config/i386/pentium.md 6 Jul 2003 22:59:41 -0000
@@ -210,7 +210,7 @@
"pentium-firstv")
;; Floating point instruction dispatch in U pipe, but continue
-;; in FP pipeline allowing other isntructions to be executed.
+;; in FP pipeline allowing other instructions to be executed.
(define_insn_reservation "pent_fp" 3
(and (eq_attr "cpu" "pentium")
(eq_attr "type" "fop,fistp"))
Index: config/ia64/ia64.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.c,v
retrieving revision 1.235
diff -u -r1.235 ia64.c
--- config/ia64/ia64.c 2 Jul 2003 21:33:54 -0000 1.235
+++ config/ia64/ia64.c 6 Jul 2003 22:59:44 -0000
@@ -1559,7 +1559,7 @@
bool addr_dead_p;
/* ??? We are currently constrained to *not* use peep2, because
- we can legitimiately change the global lifetime of the GP
+ we can legitimately change the global lifetime of the GP
(in the form of killing where previously live). This is
because a call through a descriptor doesn't use the previous
value of the GP, while a direct call does, and we do not
Index: config/ia64/itanium1.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/itanium1.md,v
retrieving revision 1.3
diff -u -r1.3 itanium1.md
--- config/ia64/itanium1.md 13 Mar 2003 18:26:30 -0000 1.3
+++ config/ia64/itanium1.md 6 Jul 2003 22:59:45 -0000
@@ -178,7 +178,7 @@
first regular expression *and* the reservation described by
the second regular expression *and* etc.
- 4. "*" is used for convinience and simply means sequence in
+ 4. "*" is used for convenience and simply means sequence in
which the regular expression are repeated NUMBER times with
cycle advancing (see ",").
@@ -461,7 +461,7 @@
(define_reservation "1_F" "1_F0|1_F1|1_F2")
;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
-;;; unit. That is, a B slot in 1st position is despersed to B0. In the
+;;; unit. That is, a B slot in 1st position is dispersed to B0. In the
;;; 2nd position it is dispersed to B2".
(define_reservation "1_NB"
"1_0b.bb+1_unb0|1_0bb.b+1_unb1|1_0bbb.+1_unb2\
@@ -908,7 +908,7 @@
;; Bypasses:
(define_bypass 1 "1_fcmp" "1_br,1_scall")
-;; ??? I found 7 cycle dealy for 1_fmac -> 1_fcmp for Itanium1
+;; ??? I found 7 cycle delay for 1_fmac -> 1_fcmp for Itanium1
(define_bypass 7 "1_fmac" "1_fmisc,1_fcvtfx,1_xmpy,1_fcmp")
;; ???
@@ -1235,7 +1235,7 @@
|1b_1mf.i+1_5+1b_uf1|1b_1mf.b+1_5+1b_uf1")
;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
-;;; unit. That is, a B slot in 1st position is despersed to B0. In the
+;;; unit. That is, a B slot in 1st position is dispersed to B0. In the
;;; 2nd position it is dispersed to B2".
(define_reservation "1b_NB"
"1b_0b.bb+1_1+1b_unb0|1b_0bb.b+1_2+1b_unb1|1b_0bbb.+1_3+1b_unb2\
Index: config/ia64/itanium2.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/itanium2.md,v
retrieving revision 1.4
diff -u -r1.4 itanium2.md
--- config/ia64/itanium2.md 2 Jul 2003 21:33:54 -0000 1.4
+++ config/ia64/itanium2.md 6 Jul 2003 22:59:46 -0000
@@ -176,7 +176,7 @@
first regular expression *and* the reservation described by
the second regular expression *and* etc.
- 4. "*" is used for convinience and simply means sequence in
+ 4. "*" is used for convenience and simply means sequence in
which the regular expression are repeated NUMBER times with
cycle advancing (see ",").
@@ -524,7 +524,7 @@
(define_reservation "2_F" "2_F0|2_F1|2_F2")
;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
-;;; unit. That is, a B slot in 1st position is despersed to B0. In the
+;;; unit. That is, a B slot in 1st position is dispersed to B0. In the
;;; 2nd position it is dispersed to B2".
(define_reservation "2_NB"
"2_0b.bb+2_unb0|2_0bb.b+2_unb1|2_0bbb.+2_unb2\
@@ -1349,7 +1349,7 @@
|2b_1mf.i+2_5+2b_uf1|2b_1mmf.+2_6+2b_uf1|2b_1mf.b+2_5+2b_uf1")
;;; "Each B slot in MBB or BBB bundle disperses to the corresponding B
-;;; unit. That is, a B slot in 1st position is despersed to B0. In the
+;;; unit. That is, a B slot in 1st position is dispersed to B0. In the
;;; 2nd position it is dispersed to B2".
(define_reservation "2b_NB"
"2b_0b.bb+2_1+2b_unb0|2b_0bb.b+2_2+2b_unb1|2b_0bbb.+2_3+2b_unb2\
Index: config/m32r/m32r.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m32r/m32r.md,v
retrieving revision 1.28
diff -u -r1.28 m32r.md
--- config/m32r/m32r.md 17 Jun 2003 19:03:11 -0000 1.28
+++ config/m32r/m32r.md 6 Jul 2003 22:59:47 -0000
@@ -204,7 +204,7 @@
;; Function units of the M32R
;; Units that take one cycle do not need to be specified.
-;; (define_function_unit {name} {multiplicity} {simulataneity} {test}
+;; (define_function_unit {name} {multiplicity} {simultaneity} {test}
;; {ready-delay} {issue-delay} [{conflict-list}])
;; Hack to get GCC to better pack the instructions.
@@ -2537,7 +2537,7 @@
;; st r4,@(4,sp)
;; bl sub
;;
-;; Simialr code is produced for the subtract expression. With this
+;; Similar code is produced for the subtract expression. With this
;; peephole the redundant move is eliminated.
;;
;; This optimization only works if PRESERVE_DEATH_INFO_REGNO_P is
Index: config/m68hc11/m68hc11.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/m68hc11/m68hc11.c,v
retrieving revision 1.84
diff -u -r1.84 m68hc11.c
--- config/m68hc11/m68hc11.c 3 Jul 2003 12:34:06 -0000 1.84
+++ config/m68hc11/m68hc11.c 6 Jul 2003 22:59:49 -0000
@@ -5185,7 +5185,7 @@
if (optimize)
compute_bb_for_insn ();
- /* After some splitting, there are some oportunities for CSE pass.
+ /* After some splitting, there are some opportunities for CSE pass.
This happens quite often when 32-bit or above patterns are split. */
if (optimize > 0 && split_done)
{
Index: config/mcore/mcore.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mcore/mcore.c,v
retrieving revision 1.48
diff -u -r1.48 mcore.c
--- config/mcore/mcore.c 3 Jul 2003 12:34:07 -0000 1.48
+++ config/mcore/mcore.c 6 Jul 2003 22:59:50 -0000
@@ -2651,7 +2651,7 @@
/* The maximum number of constants that can fit into one pool, since
the pc relative range is 0...1020 bytes and constants are at least 4
- bytes long. We subtact 4 from the range to allow for the case where
+ bytes long. We subtract 4 from the range to allow for the case where
we need to add a branch/align before the constant pool. */
#define MAX_COUNT 1016
Index: config/mips/sr71k.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/sr71k.md,v
retrieving revision 1.3
diff -u -r1.3 sr71k.md
--- config/mips/sr71k.md 1 May 2003 02:33:13 -0000 1.3
+++ config/mips/sr71k.md 6 Jul 2003 22:59:50 -0000
@@ -2,7 +2,7 @@
;;
;; DFA-based pipeline description for Sandcraft SR3 (MIPS64 based)
;;
-;; The SR3 is describeds as:
+;; The SR3 is described as:
;; - nine-stage pipeline, insn buffering with out-of-order issue to
;; multiple function units, with an average dispatch rate of 2
;; insn.s per cycle (max 6 insns: 2 fpu, 4 cpu).
@@ -22,8 +22,8 @@
;;
;;
;; Reservation model is based on:
-;; 1) Figure 6-1, from the 1.0 specicification.
-;; 2) Chapter 19, from the 1.0 specificication.
+;; 1) Figure 6-1, from the 1.0 specification.
+;; 2) Chapter 19, from the 1.0 specification.
;; 3) following questions(Red Hat)/answers(Sandcraft):
;; RH> From Section 19.1
;; RH> 1) In terms of figure 6-1, are all the instructions in
Index: config/mips/t-iris5-as
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/t-iris5-as,v
retrieving revision 1.1
diff -u -r1.1 t-iris5-as
--- config/mips/t-iris5-as 11 Jul 2002 18:56:56 -0000 1.1
+++ config/mips/t-iris5-as 6 Jul 2003 22:59:50 -0000
@@ -1,5 +1,5 @@
# omit -g, gcc doesn't support the o32 mdebug debugging format and warns about
-# every invokation with -g*
+# every invocation with -g*
# add -save-temps to avoid comparison failure due to embedded temp file names
BOOT_CFLAGS = -O2 -save-temps
Index: config/mmix/mmix.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mmix/mmix.h,v
retrieving revision 1.57
diff -u -r1.57 mmix.h
--- config/mmix/mmix.h 30 Jun 2003 21:11:43 -0000 1.57
+++ config/mmix/mmix.h 6 Jul 2003 22:59:51 -0000
@@ -169,7 +169,7 @@
address goes in a global register. When addressing, it's more like
"base address plus offset", with the offset being 0..255 from the base,
which itself can be a symbol plus an offset. The effect is like having
- a constant pool in global registers, code offseting from those
+ a constant pool in global registers, code offsetting from those
registers (automatically causing a request for a suitable constant base
address register) without having to know the specific register or the
specific offset. The setback is that there's a limited number of
Index: config/ns32k/NOTES
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ns32k/NOTES,v
retrieving revision 1.3
diff -u -r1.3 NOTES
--- config/ns32k/NOTES 17 Jun 2003 19:03:12 -0000 1.3
+++ config/ns32k/NOTES 6 Jul 2003 22:59:51 -0000
@@ -53,7 +53,7 @@
which is, in effect, "branch if ordered and less than."
We also need insns for the reverse branches. These have the PC and
-the label ref opereands reversed. Thus the reverse bgt has a pattern:
+the label ref operands reversed. Thus the reverse bgt has a pattern:
(set (pc)
(if_then_else (gt (cc0)
Index: config/ns32k/ns32k.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ns32k/ns32k.h,v
retrieving revision 1.57
diff -u -r1.57 ns32k.h
--- config/ns32k/ns32k.h 19 Jun 2003 21:47:19 -0000 1.57
+++ config/ns32k/ns32k.h 6 Jul 2003 22:59:52 -0000
@@ -472,7 +472,7 @@
/* LONG_REGS are registers which can only hold double precision floats
- * and can only be accessable by long float instructions.
+ * and can only be accessible by long float instructions.
*/
#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
(GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
@@ -885,7 +885,7 @@
#endif
/* SMALL_REGISTER_CLASSES is a run time option. This should no longer
- be necessay and should go when we have confidence that we won't run
+ be necessary and should go when we have confidence that we won't run
out of spill registers */
#define SMALL_REGISTER_CLASSES (target_flags & MASK_SRC)