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Fix recent SPEC2000/x86-64 ICEs
- From: Jan Hubicka <jh at suse dot cz>
- To: gcc-patches at gcc dot gnu dot org, rth at redhat dot com, roger at eyesopen dot com
- Date: Mon, 30 Jun 2003 01:06:01 +0200
- Subject: Fix recent SPEC2000/x86-64 ICEs
Hi,
Roger's patches to add math builtins are not working very well on x86-64
where we use TARGET_128BIT_LONG_DOUBLE so we must use TFmode instead.
Bootstrapped/regtested i386, OK?
Honza
Mon Jun 30 00:52:08 CEST 2003 Jan Hubicka <jh@suse.cz>
* i386.c (standard_80387_constant_p): Accept TFmode constants too.
* i386.md (atanxf): Disable for TARGET_128BIT_LONG_LONG
(atantf): Disable for !TARGET_128BIT_LONG_LONG
(fyl2x_sfxf3, fyl2x_dfxf3): Accept TFmode operands.
(fyl2x_xfxf3, fyl2x_tfxf3): Enable/disable as needed.
(fscale_sfxf3, fscale_dfxf3): Accept TFmode operands.
(fscale_xfxf3, fscale_tfxf3): Enable/disable as needed.
(frndinttf2): New.
(f2xm1tf2): New.
(exp?f2): Use expsf2_tf when needed.
(exp?f2_tf): New.
(exptf): New.
Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.581
diff -c -3 -p -r1.581 i386.c
*** config/i386/i386.c 25 Jun 2003 22:28:26 -0000 1.581
--- config/i386/i386.c 29 Jun 2003 22:48:12 -0000
*************** standard_80387_constant_p (x)
*** 4316,4322 ****
/* For XFmode constants, try to find a special 80387 instruction on
those CPUs that benefit from them. */
! if (GET_MODE (x) == XFmode
&& x86_ext_80387_constants & TUNEMASK)
{
REAL_VALUE_TYPE r;
--- 4316,4322 ----
/* For XFmode constants, try to find a special 80387 instruction on
those CPUs that benefit from them. */
! if ((GET_MODE (x) == XFmode || GET_MODE (x) == TFmode)
&& x86_ext_80387_constants & TUNEMASK)
{
REAL_VALUE_TYPE r;
Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.472
diff -c -3 -p -r1.472 i386.md
*** config/i386/i386.md 25 Jun 2003 22:28:27 -0000 1.472
--- config/i386/i386.md 29 Jun 2003 22:48:12 -0000
***************
*** 15613,15619 ****
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
--- 15613,15619 ----
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
***************
*** 15625,15631 ****
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
--- 15625,15631 ----
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"fpatan"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
***************
*** 15633,15643 ****
(define_insn "*fyl2x_sfxf3"
[(parallel [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 2 "register_operand" "0")
! (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2X))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
--- 15633,15644 ----
(define_insn "*fyl2x_sfxf3"
[(parallel [(set (match_operand:SF 0 "register_operand" "=f")
(unspec:SF [(match_operand:SF 2 "register_operand" "0")
! (match_operand 1 "register_operand" "u")]
UNSPEC_FYL2X))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations
! && GET_MODE (operands[1]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
***************
*** 15645,15655 ****
(define_insn "*fyl2x_dfxf3"
[(parallel [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 2 "register_operand" "0")
! (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FYL2X))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")])
--- 15646,15657 ----
(define_insn "*fyl2x_dfxf3"
[(parallel [(set (match_operand:DF 0 "register_operand" "=f")
(unspec:DF [(match_operand:DF 2 "register_operand" "0")
! (match_operand 1 "register_operand" "u")]
UNSPEC_FYL2X))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations
! && GET_MODE (operands[1]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")])
***************
*** 15661,15667 ****
UNSPEC_FYL2X))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
--- 15663,15669 ----
UNSPEC_FYL2X))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
***************
*** 15673,15679 ****
UNSPEC_FYL2X))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
--- 15675,15681 ----
UNSPEC_FYL2X))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"fyl2x"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
***************
*** 15714,15720 ****
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_dup 2))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
{
rtx temp;
--- 15716,15722 ----
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_dup 2))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
{
rtx temp;
***************
*** 15729,15735 ****
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_dup 2))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
{
rtx temp;
--- 15731,15737 ----
(match_dup 2)] UNSPEC_FYL2X))
(clobber (match_dup 2))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
{
rtx temp;
***************
*** 15740,15763 ****
(define_insn "*fscale_sfxf3"
[(parallel [(set (match_operand:SF 0 "register_operand" "=f")
! (unspec:SF [(match_operand:XF 2 "register_operand" "0")
! (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FSCALE))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"fscale\;fstp\t%y1"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
(define_insn "*fscale_dfxf3"
[(parallel [(set (match_operand:DF 0 "register_operand" "=f")
! (unspec:DF [(match_operand:XF 2 "register_operand" "0")
! (match_operand:XF 1 "register_operand" "u")]
UNSPEC_FSCALE))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"fscale\;fstp\t%y1"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")])
--- 15742,15769 ----
(define_insn "*fscale_sfxf3"
[(parallel [(set (match_operand:SF 0 "register_operand" "=f")
! (unspec:SF [(match_operand 2 "register_operand" "0")
! (match_operand 1 "register_operand" "u")]
UNSPEC_FSCALE))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations
! && GET_MODE (operands[1]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode
! && GET_MODE (operands[2]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode"
"fscale\;fstp\t%y1"
[(set_attr "type" "fpspc")
(set_attr "mode" "SF")])
(define_insn "*fscale_dfxf3"
[(parallel [(set (match_operand:DF 0 "register_operand" "=f")
! (unspec:DF [(match_operand 2 "register_operand" "0")
! (match_operand 1 "register_operand" "u")]
UNSPEC_FSCALE))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations
! && GET_MODE (operands[1]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode
! && GET_MODE (operands[2]) == TARGET_128BIT_LONG_DOUBLE ? TFmode : XFmode"
"fscale\;fstp\t%y1"
[(set_attr "type" "fpspc")
(set_attr "mode" "DF")])
***************
*** 15769,15775 ****
UNSPEC_FSCALE))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"fscale\;fstp\t%y1"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
--- 15775,15793 ----
UNSPEC_FSCALE))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
! "fscale\;fstp\t%y1"
! [(set_attr "type" "fpspc")
! (set_attr "mode" "XF")])
!
! (define_insn "*fscale_tf3"
! [(parallel [(set (match_operand:TF 0 "register_operand" "=f")
! (unspec:TF [(match_operand:TF 2 "register_operand" "0")
! (match_operand:TF 1 "register_operand" "u")]
! UNSPEC_FSCALE))
! (clobber (match_dup 1))])]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"fscale\;fstp\t%y1"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
***************
*** 15779,15785 ****
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_FRNDINT))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"frndint"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
--- 15797,15813 ----
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_FRNDINT))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
! "frndint"
! [(set_attr "type" "fpspc")
! (set_attr "mode" "XF")])
!
! (define_insn "*frndinttf2"
! [(set (match_operand:TF 0 "register_operand" "=f")
! (unspec:TF [(match_operand:TF 1 "register_operand" "0")]
! UNSPEC_FRNDINT))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"frndint"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
***************
*** 15789,15795 ****
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_F2XM1))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
"f2xm1"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
--- 15817,15833 ----
(unspec:XF [(match_operand:XF 1 "register_operand" "0")]
UNSPEC_F2XM1))]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
! "f2xm1"
! [(set_attr "type" "fpspc")
! (set_attr "mode" "XF")])
!
! (define_insn "*f2xm1tf2"
! [(set (match_operand:TF 0 "register_operand" "=f")
! (unspec:TF [(match_operand:TF 1 "register_operand" "0")]
! UNSPEC_F2XM1))]
! "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
"f2xm1"
[(set_attr "type" "fpspc")
(set_attr "mode" "XF")])
***************
*** 15811,15816 ****
--- 15849,15860 ----
rtx temp;
int i;
+ if (TARGET_128BIT_LONG_DOUBLE)
+ {
+ emit_insn (gen_expsf2_tf (operands[0], operands[1]));
+ DONE;
+ }
+
for (i=2; i<10; i++)
operands[i] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */
***************
*** 15818,15823 ****
--- 15862,15891 ----
emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
})
+ (define_expand "expsf2_tf"
+ [(set (match_dup 2)
+ (float_extend:TF (match_operand:SF 1 "register_operand" "")))
+ (set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3)))
+ (set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT))
+ (set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5)))
+ (set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1))
+ (set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8)))
+ (parallel [(set (match_operand:SF 0 "register_operand" "")
+ (unspec:SF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
+ (clobber (match_dup 5))])]
+ ""
+ {
+ rtx temp;
+ int i;
+
+ for (i=2; i<10; i++)
+ operands[i] = gen_reg_rtx (TFmode);
+ temp = simplify_unary_operation (FLOAT_EXTEND, TFmode,
+ standard_80387_constant_rtx (5), XFmode); /* fldl2e */
+ emit_move_insn (operands[3], temp);
+ emit_move_insn (operands[8], CONST1_RTX (TFmode)); /* fld1 */
+ })
+
(define_expand "expdf2"
[(set (match_dup 2)
(float_extend:XF (match_operand:DF 1 "register_operand" "")))
***************
*** 15835,15840 ****
--- 15903,15914 ----
rtx temp;
int i;
+ if (TARGET_128BIT_LONG_DOUBLE)
+ {
+ emit_insn (gen_expdf2_tf (operands[0], operands[1]));
+ DONE;
+ }
+
for (i=2; i<10; i++)
operands[i] = gen_reg_rtx (XFmode);
temp = standard_80387_constant_rtx (5); /* fldl2e */
***************
*** 15842,15847 ****
--- 15916,15946 ----
emit_move_insn (operands[8], CONST1_RTX (XFmode)); /* fld1 */
})
+
+ (define_expand "expdf2_tf"
+ [(set (match_dup 2)
+ (float_extend:TF (match_operand:DF 1 "register_operand" "")))
+ (set (match_dup 4) (mult:TF (match_dup 2) (match_dup 3)))
+ (set (match_dup 5) (unspec:TF [(match_dup 4)] UNSPEC_FRNDINT))
+ (set (match_dup 6) (minus:TF (match_dup 4) (match_dup 5)))
+ (set (match_dup 7) (unspec:TF [(match_dup 6)] UNSPEC_F2XM1))
+ (set (match_dup 9) (plus:TF (match_dup 7) (match_dup 8)))
+ (parallel [(set (match_operand:DF 0 "register_operand" "")
+ (unspec:DF [(match_dup 9) (match_dup 5)] UNSPEC_FSCALE))
+ (clobber (match_dup 5))])]
+ ""
+ {
+ rtx temp;
+ int i;
+
+ for (i=2; i<10; i++)
+ operands[i] = gen_reg_rtx (TFmode);
+ temp = simplify_unary_operation (FLOAT_EXTEND, TFmode,
+ standard_80387_constant_rtx (5), XFmode); /* fldl2e */
+ emit_move_insn (operands[3], temp);
+ emit_move_insn (operands[8], CONST1_RTX (TFmode)); /* fld1 */
+ })
+
(define_expand "expxf2"
[(set (match_dup 3) (mult:XF (match_operand:XF 1 "register_operand" "")
(match_dup 2)))
***************
*** 15853,15859 ****
(unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
(clobber (match_dup 4))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
{
rtx temp;
int i;
--- 15952,15958 ----
(unspec:XF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
(clobber (match_dup 4))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
{
rtx temp;
int i;
***************
*** 15878,15883 ****
--- 15977,16005 ----
emit_move_insn (operands[2], CONST1_RTX (SFmode)); /* fld1 */
})
+ (define_expand "exptf2"
+ [(set (match_dup 3) (mult:TF (match_operand:TF 1 "register_operand" "")
+ (match_dup 2)))
+ (set (match_dup 4) (unspec:TF [(match_dup 3)] UNSPEC_FRNDINT))
+ (set (match_dup 5) (minus:TF (match_dup 3) (match_dup 4)))
+ (set (match_dup 6) (unspec:TF [(match_dup 5)] UNSPEC_F2XM1))
+ (set (match_dup 8) (plus:TF (match_dup 6) (match_dup 7)))
+ (parallel [(set (match_operand:TF 0 "register_operand" "")
+ (unspec:TF [(match_dup 8) (match_dup 4)] UNSPEC_FSCALE))
+ (clobber (match_dup 4))])]
+ "! TARGET_NO_FANCY_MATH_387 && TARGET_80387
+ && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
+ {
+ rtx temp;
+ int i;
+
+ for (i=2; i<9; i++)
+ operands[i] = gen_reg_rtx (TFmode);
+ temp = standard_80387_constant_rtx (5); /* fldl2e */
+ emit_move_insn (operands[2], temp);
+ emit_move_insn (operands[7], CONST1_RTX (TFmode)); /* fld1 */
+ })
+
(define_expand "atandf2"
[(parallel [(set (match_operand:DF 0 "register_operand" "")
(unspec:DF [(match_dup 2)
***************
*** 15898,15904 ****
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (XFmode);
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
--- 16020,16026 ----
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && !TARGET_128BIT_LONG_DOUBLE"
{
operands[2] = gen_reg_rtx (XFmode);
emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */
***************
*** 15911,15917 ****
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations"
{
operands[2] = gen_reg_rtx (TFmode);
emit_move_insn (operands[2], CONST1_RTX (TFmode)); /* fld1 */
--- 16033,16039 ----
UNSPEC_FPATAN))
(clobber (match_dup 1))])]
"! TARGET_NO_FANCY_MATH_387 && TARGET_80387
! && flag_unsafe_math_optimizations && TARGET_128BIT_LONG_DOUBLE"
{
operands[2] = gen_reg_rtx (TFmode);
emit_move_insn (operands[2], CONST1_RTX (TFmode)); /* fld1 */