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Re: target register load optimizations
On Mon, Jun 09, 2003 at 09:00:00PM -0400, Daniel Berlin wrote:
> >Is there anything you're doing here that wouldn't be solved with a
> >register allocator that placed spill/fill code at optimal locations?
>
> This is an NP-complete problem too, though easier to model using ILP.
> See "Optimal spilling for CISC machines with few registers"
Um, well, yeah, I guess that's true. The particular sub-problem I was
thinking about is slightly less complicated than that.
Namely, all inputs are constants (so no spill, only fill), and I didn't
really mean "optimial" so much as "not stupid". Stuff well within the
bounds of current register allocation passes.
r~