[PATCH]: Fix PA CCFP placeholder ICE (PR 8705)

["John David Anglin" <dave at hiauly1 dot hia dot nrc dot ca>]

The enclosed patch fixes the ICE that occurs for the following test
program from PR 8705:

void foo(void)
{
  double a=0, eps=0;
  while (eps) a-=1;
}

This was first reported on the hppa64-hpux port on the 3.1/3.2 branch,
but it affects all PA ports.

The ICE occurs when the loop pass attempts to move a set of the
CCFP condition code register out of the loop.  For example,

(insn 42 9 43 0 7afe0930 (set (reg:CCFP 0 %r0)
        (const_int 0 [0x0])) 2 {*movccfp0} (nil)
    (nil))

The occurs even without the placeholder sets.  They were introduced
into 3.3 last fall.  As we didn't have an expander to handle such
things, emit_move_insn_1 tried various fallback options.  In the
64-bit case, there weren't any because the size of the condition
code modes is smaller that the word size.

So, the patch adds an expander and fixes the conditions used in
the placeholder instructions.  They need to be reversed like the
conditions for the Y constraint.  I should fix that sillyness.

I have tested the fix on hppa2.0w-hp-hpux11.11, hppa64-hp-hpux11.11
and hppa-unknown-linux-gnu with no regressions.  The patch has
been installed to 3.3 and main.

However, the problems that caused the ICE are not fixed, so I am
not closing the PR.

1) I don't believe that the loop pass should be moving CC_MODE
   sets out of loops.  As far as I can tell, the only pass that
   can simplify conditional jumps is the combine pass.  I believe
   that this can only happen if the CC_MODE set and jump stay
   together.

2) The CSE pass can't simplify conditional jumps involving
   CC_MODE registers because gen_lowpart_common doesn't handle
   CC_MODE.  As a result, the state of a CC_MODE register doesn't
   get recorded and the if_then_else can't be simplified.

I noticed that ia64 appears to use BImode for floating point
compares.  A quick switch from CCFPmode to BImode seemed encouraging
as far as code elimination goes.  For example, function foo in
the above testcase drops from 10 to 1 instruction at -O2.  It
looks like treating the the floating point status register as
a separate predicate register would be beneficial in terms of
floating point code optimization.

Dave
-- 
J. David Anglin                                  dave dot anglin at nrc-cnrc dot gc dot ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)

2003-04-20  John David Anglin  <dave dot anglin at nrc-cnrc dot gc dot ca>

	PR/8705
	* pa.md (movccfp): New expander.
	(setccfp0, setccfp1): Rename to movccfp0 and movccfp1, respectively.
	Reverse fcmp conditions.

Index: config/pa/pa.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.md,v
retrieving revision 1.116.2.7
diff -u -3 -p -r1.116.2.7 pa.md
--- config/pa/pa.md	19 Mar 2003 05:07:27 -0000	1.116.2.7
+++ config/pa/pa.md	19 Apr 2003 20:20:42 -0000
@@ -625,23 +625,37 @@
   [(set_attr "length" "4")
    (set_attr "type" "fpcc")])
 
-;; The following two patterns are optimization placeholders.  In almost
+;; Provide a means to emit the movccfp0 and movccfp1 optimization
+;; placeholders.  This is necessary in rare situations when a
+;; placeholder is re-emitted (see PR 8705).
+
+(define_expand "movccfp"
+  [(set (reg:CCFP 0)
+	(match_operand 0 "const_int_operand" ""))]
+  "! TARGET_SOFT_FLOAT"
+  "
+{
+  if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
+    FAIL;
+}")
+
+;; The following patterns are optimization placeholders.  In almost
 ;; all cases, the user of the condition code will be simplified and the
 ;; original condition code setting insn should be eliminated.
 
-(define_insn "*setccfp0"
+(define_insn "*movccfp0"
   [(set (reg:CCFP 0)
 	(const_int 0))]
   "! TARGET_SOFT_FLOAT"
-  "fcmp,dbl,!= %%fr0,%%fr0"
+  "fcmp,dbl,= %%fr0,%%fr0"
   [(set_attr "length" "4")
    (set_attr "type" "fpcc")])
 
-(define_insn "*setccfp1"
+(define_insn "*movccfp1"
   [(set (reg:CCFP 0)
 	(const_int 1))]
   "! TARGET_SOFT_FLOAT"
-  "fcmp,dbl,= %%fr0,%%fr0"
+  "fcmp,dbl,!= %%fr0,%%fr0"
   [(set_attr "length" "4")
    (set_attr "type" "fpcc")])