Re: PR 10017

[Richard Henderson <rth at redhat dot com>]

On Mon, Mar 31, 2003 at 10:22:53AM -0800, Mark Mitchell wrote:
> Do you consider 10017 to be a bug, or invalid user input?

I dunno.  I'm inclined to think user error.  This works
without -march=i686 because there we generate

        shldl   %eax, %edx
        sall    %cl, %eax
        testb   $32, %cl
        je      .L8
        movl    %eax, %edx
        xorl	%eax, %eax
.L8:

which has *exactly* the right number of registers free.
With -march=i686 we prefer

	xorl	%ebx, %ebx
        shldl   %eax, %edx
        sall    %cl, %eax
        testb   $32, %cl
	cmovne	%eax, %edx
	cmovne	%ebx, %edx

which uses one more register.  I *do* have a patch that tries
to scavange a free register when available instead of forcing
reload to find us one.  It does work for this case, but it
also can't allocate *new* registers at this point, so for 
a lot of cases it fails to generate the cmove at all.  I'm
not sure I want to penalize more common code for this edge case.

For the record, here's the patch.


r~



Index: i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.404.2.13
diff -c -p -d -r1.404.2.13 i386.md
*** i386.md	25 Mar 2003 10:30:28 -0000	1.404.2.13
--- i386.md	31 Mar 2003 20:18:01 -0000
***************
*** 10343,10353 ****
  	      (clobber (reg:CC 17))])]
    ""
  {
-   if (!TARGET_64BIT && TARGET_CMOVE && ! immediate_operand (operands[2], QImode))
-     {
-       emit_insn (gen_ashldi3_1 (operands[0], operands[1], operands[2]));
-       DONE;
-     }
    ix86_expand_binary_operator (ASHIFT, DImode, operands);
    DONE;
  })
--- 10343,10348 ----
***************
*** 10454,10496 ****
  	   (const_string "ishift")))
     (set_attr "mode" "DI")])
  
! (define_insn "ashldi3_1"
!   [(set (match_operand:DI 0 "register_operand" "=r")
! 	(ashift:DI (match_operand:DI 1 "register_operand" "0")
! 		   (match_operand:QI 2 "nonmemory_operand" "Jc")))
!    (clobber (match_scratch:SI 3 "=&r"))
!    (clobber (reg:CC 17))]
!   "!TARGET_64BIT && TARGET_CMOVE"
!   "#"
!   [(set_attr "type" "multi")])
! 
! (define_insn "*ashldi3_2"
    [(set (match_operand:DI 0 "register_operand" "=r")
  	(ashift:DI (match_operand:DI 1 "register_operand" "0")
  		   (match_operand:QI 2 "nonmemory_operand" "Jc")))
     (clobber (reg:CC 17))]
    "!TARGET_64BIT"
    "#"
    [(set_attr "type" "multi")])
  
! (define_split
!   [(set (match_operand:DI 0 "register_operand" "")
! 	(ashift:DI (match_operand:DI 1 "register_operand" "")
! 		   (match_operand:QI 2 "nonmemory_operand" "")))
!    (clobber (match_scratch:SI 3 ""))
!    (clobber (reg:CC 17))]
!   "!TARGET_64BIT && TARGET_CMOVE && reload_completed"
    [(const_int 0)]
    "ix86_split_ashldi (operands, operands[3]); DONE;")
- 
- (define_split
-   [(set (match_operand:DI 0 "register_operand" "")
- 	(ashift:DI (match_operand:DI 1 "register_operand" "")
- 		   (match_operand:QI 2 "nonmemory_operand" "")))
-    (clobber (reg:CC 17))]
-   "!TARGET_64BIT && reload_completed"
-   [(const_int 0)]
-   "ix86_split_ashldi (operands, NULL_RTX); DONE;")
  
  (define_insn "x86_shld_1"
    [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")
--- 10449,10479 ----
  	   (const_string "ishift")))
     (set_attr "mode" "DI")])
  
! (define_insn_and_split "*ashldi3_2"
    [(set (match_operand:DI 0 "register_operand" "=r")
  	(ashift:DI (match_operand:DI 1 "register_operand" "0")
  		   (match_operand:QI 2 "nonmemory_operand" "Jc")))
     (clobber (reg:CC 17))]
    "!TARGET_64BIT"
    "#"
+   "&& reload_completed
+    && (! TARGET_CMOVE
+        || !REG_P (operands[2])
+        || !flag_peephole2
+        || flow2_completed)"
+   [(const_int 0)]
+   "ix86_split_ashldi (operands, NULL_RTX); DONE;"
    [(set_attr "type" "multi")])
  
! (define_peephole2
!   [(match_scratch:SI 3 "r")
!    (parallel [(set (match_operand:DI 0 "register_operand" "")
! 		   (ashift:DI (match_operand:DI 1 "register_operand" "")
! 			      (match_operand:QI 2 "register_operand" "")))
! 	      (clobber (reg:CC 17))])]
!   "!TARGET_64BIT && TARGET_CMOVE"
    [(const_int 0)]
    "ix86_split_ashldi (operands, operands[3]); DONE;")
  
  (define_insn "x86_shld_1"
    [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m,r*m")