PATCH for [ARM] subsequent use of plus and minus operators couldbe improved

[Gábor Lóki <alga at rgai dot hu>]

This patch solves the "[ARM] subsequent use of plus and
minus operators could be improved" PR.

http://gcc.gnu.org/cgi-bin/gnatsweb.pl?cmd=view%20audit-trail&database=gcc&pr=10242

This patch uses peephole pattern to simplify subsequent
plus-minus operators.

It also includes peepholes for special cases of set register
with "x - 0" or "x + 0".

Example source code:

void func(char*);
void foo()
{
   char buf[1028];
   func(buf);
}

Original [ARM] code:

foo:
     mov    ip, sp
     stmfd    sp!, {fp, ip, lr, pc}
     sub    fp, ip, #4
     sub    r0, fp, #1024
     sub    sp, sp, #1024
     sub    sp, sp, #4
     sub    r0, r0, #12
     sub    r0, r0, #4
     bl    func
     ldmea    fp, {fp, sp, pc}

Patched [ARM] code:

foo:
     mov    ip, sp
     stmfd    sp!, {fp, ip, lr, pc}
     sub    fp, ip, #4
     sub    sp, sp, #1024
     sub    sp, sp, #4
     sub    r0, fp, #1024
     sub    r0, r0, #16
     bl    func
     ldmea    fp, {fp, sp, pc}

Change log entry:

2003-03-31 Gabor Loki <alga at rgai dot hu>

	* New peepholes to simplify subsequent plus-minus
	  operators in ARM.


regtested:
arm-unknown-elf with gcc version 3.3 20030324 (prerelease)

Patch attached for gcc-20030324.

Regards,
     Gábor Lóki

diff -Nrc3pad gcc-20030324.orig/gcc/config/arm/arm.md gcc-20030324/gcc/config/arm/arm.md
*** gcc-20030324.orig/gcc/config/arm/arm.md Thu Mar 20 23:03:17 2003
--- gcc-20030324/gcc/config/arm/arm.md  Thu Mar 27 11:18:30 2003
***************
*** 8542,8547 ****
--- 8542,8623 ----
    ""
  )
  
+ ; These patterns combine two register manipulation insns, combine can't do that
+ 
+ (define_peephole2
+   [(set (match_operand:SI 0 "s_register_operand" "")
+         (plus:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "const_int_operand"  "")))
+    (set (match_dup 0)
+         (plus:SI (match_dup 0) (match_operand:SI 3 "const_int_operand"  "")))]
+   "TARGET_ARM && (const_ok_for_arm(XINT(operands[2],0) + XINT(operands[3],0)) || const_ok_for_arm(-XINT(operands[2],0) - XINT(operands[3],0)))
+   "
+   [(set (match_dup 0)
+         (plus:SI (match_dup 1) (match_dup 4)))]
+   "
+     operands[4] = GEN_INT (XINT(operands[2],0) + XINT(operands[3],0));
+   "
+ )
+ 
+ (define_peephole2
+   [(set (match_operand:SI 0 "s_register_operand" "")
+         (minus:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "const_int_operand"  "")))
+    (set (match_dup 0)
+         (minus:SI (match_dup 0) (match_operand:SI 3 "const_int_operand"  "")))]
+   "TARGET_ARM && (const_ok_for_arm(XINT(operands[2],0) + XINT(operands[3],0)) || const_ok_for_arm(-XINT(operands[2],0) - XINT(operands[3],0)))
+   "
+   [(set (match_dup 0)
+         (minus:SI (match_dup 1) (match_dup 4)))]
+   "
+     operands[4] = GEN_INT (XINT(operands[2],0) + XINT(operands[3],0));
+   "
+ )
+ 
+ (define_peephole2
+   [(set (match_operand:SI 0 "s_register_operand" "")
+         (plus:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "const_int_operand"  "")))
+    (set (match_dup 0)
+         (minus:SI (match_dup 0) (match_operand:SI 3 "const_int_operand"  "")))]
+   "TARGET_ARM && (const_ok_for_arm(XINT(operands[2],0) - XINT(operands[3],0)) || const_ok_for_arm(-XINT(operands[2],0) + XINT(operands[3],0)))
+   "
+   [(set (match_dup 0)
+         (plus:SI (match_dup 1) (match_dup 4)))]
+   "
+     operands[4] = GEN_INT (XINT(operands[2],0) - XINT(operands[3],0));
+   "
+ )
+ 
+ (define_peephole2
+   [(set (match_operand:SI 0 "s_register_operand" "")
+         (minus:SI (match_operand:SI 1 "s_register_operand" "") (match_operand:SI 2 "const_int_operand"  "")))
+    (set (match_dup 0)
+         (plus:SI (match_dup 0) (match_operand:SI 3 "const_int_operand"  "")))]
+   "TARGET_ARM && (const_ok_for_arm(XINT(operands[3],0) - XINT(operands[2],0)) || const_ok_for_arm(-XINT(operands[3],0) + XINT(operands[2],0)))
+   "
+   [(set (match_dup 0)
+         (plus:SI (match_dup 1) (match_dup 4)))]
+   "
+     operands[4] = GEN_INT (XINT(operands[3],0) - XINT(operands[2],0));
+   "
+ )
+ 
+ (define_peephole2
+   [(set (match_operand:SI 0 "s_register_operand" "")
+         (plus:SI (match_operand:SI 1 "s_register_operand" "") (const_int 0)))]
+   "TARGET_ARM
+   "
+   [(set (match_dup 0) (match_dup 1))]
+   ""
+ )
+ 
+ (define_peephole2
+   [(set (match_operand:SI 0 "s_register_operand" "")
+         (minus:SI (match_operand:SI 1 "s_register_operand" "") (const_int 0)))]
+   "TARGET_ARM
+   "
+   [(set (match_dup 0) (match_dup 1))]
+   ""
+ )
+ 
  ; Peepholes to spot possible load- and store-multiples, if the ordering is
  ; reversed, check that the memory references aren't volatile.